Patent US5093584A successfully refreshed from Google Patents.
US5093584A
Expired / Lapsed
US
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Self calibrating timing circuit
Assignee: International Business Machines Corp
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Filing: 1991-05-06
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Granted: 1992-03-03
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Expires: 2011-05-06
Abstract
Abstract A clock circuit, together with a control current generator and a ratio circuit coupled thereto. The ratio circuit, of the invention, utilizes at least two capacitors each of which is coupled in series with a respective transistor and arranged in parallel with one another. Each capacitor transistor transistor pair is in parallel to the other and coupled between the control current generator and ground so that at least one of the transistors in a selected capacitor transistor series can be selectively turned off while the other can be directly controlled by the clock cycle. This circuit, generates timing edges within a clock cycle which timing edges can be any fraction of the clock cycle, and comprises a clock, a controlled current generator, and a ratio circuit coupled to the clock and the generator. Preferably this ratio circuit comprises at least two capacitor-transistor pairs coupled in parallel between the generator and ground with the clock being coupled to the control electrode of one of the transistors and being coupled to the control electrode of the other transistor together with a turn-off signal source. An element for discharging the capacitors is included in the circuit.
Inventors
- 👤 Justin A. Woyke
- 👤 Orest Bula
- 👤 Garrett S. Koch
- 👤 Richard S. Gomez
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 17:33
CPC Classifications
H; H03; H03L; H03L7/00; H03K; H03K5/00; H03K5/13; H03K5/133; H03K2005/00013; H03K2005/00019; H03K2005/00058; H03K2005/00065; H03K2005/00078; H03K2005/00097; H03K2005/00104; H03K2005/0015; H03K2005/00195
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
171 words
A self calibrating circuit comprising: a clock, generating a plurality of clock cycles of a selected frequency, a current generator, a test signal source, and a ratio circuit coupled to the clock, the current generator, the test signal source, and an output, said ratio circuit comprising, a pair of transistors, each transistor of said pair of transistors being coupled to the output and in series with said generator and with a respective capacitor, each transistor of said pair of transistors further having a control electrode, one transistor of said pair of transistors having its control electrode coupled to and driven by said clock, and the other of said pair of transistors having its control electrode coupled to said signal source and said clock, said other of said pair of transistors being selectively turned on by the simultaneous application of a signal from said test signal source and one clock cycle of said plurality of clock cycles, whereby said capacitor can be selectively charged switching means for discharging each of said capacitors.
Claim 2
Dependent Claim
171 words
A self calibrating circuit comprising: a clock, generating a plurality of clock cycles of a selected frequency, a current generator, a test signal source, and a ratio circuit coupled to the clock, the current generator, the test signal source, and an output, said ratio circuit comprising, a pair of transistors, each transistor of said pair of transistors being coupled to the output and in series with said generator and with a respective capacitor, each transistor of said pair of transistors further having a control electrode, one transistor of said pair of transistors having its control electrode coupled to and driven by said clock, and the other of said pair of transistors having its control electrode coupled to said signal source and said clock, said other of said pair of transistors being selectively turned on by the simultaneous application of a signal from said test signal source and one clock cycle of said plurality of clock cycles, whereby said capacitor can be selectively charged switching means for discharging each of said capacitors.
Claim 3
Dependent Claim
18 words
The circuit of claim 1 wherein said transistors and said capacitors are created in the same semiconductor chip.
Claim 4
Dependent Claim
12 words
The circuit of claim 1 wherein said capacitors of different capacitive value.
Claim 5
Dependent Claim
12 words
The circuit of claim 1 wherein said capacitors are of equal value.
Claim 6
Dependent Claim
17 words
The circuit of claim 1 wherein said means for discharging said capacitors are coupled to said clock.
Claim 7
Dependent Claim
29 words
The circuit of claim 1 wherein the other of said pair of transistors is coupled to and driven by the clock and the signal source through an AND circuit.
Claim 8
Dependent Claim
25 words
The circuit of claim 1 wherein there is further provided an operational amplifier coupled to said pair of transistors and to a reference voltage source.
Claim 9
Dependent Claim
18 words
The circuit of claim 1 wherein said current generator includes means for producing current over varying time sequences.
Claim 10
Dependent Claim
23 words
The circuit of claim 1 wherein there is further provided counter means coupled to said current generator means for decrementing said current generator.
Claim 11
Dependent Claim
174 words
A circuit for generating timing edges within a clock cycle comprising: clock means, means for generating a controlled current, and a ratio circuit coupled to an output, said clock means and said generating means, said ratio circuit comprising; at least two capacitors and two transistors, each of said transistors having a control electrode, each of said capacitors being coupled in series with a respective transistor to form a respective capacitor transistor series, each one of said capacitor transistor series being coupled in parallel between said controlled current generating means and ground, said clock means being directly coupled to the control electrode of the transistor of one of said capacitor transistor series whereby the capacitor to said one of said capacitor transistor series can be charged, means coupled to the control electrode of the transistor in the other of said capacitor transistor series for selectively turning off the transistor in the other of said capacitor transistor series, whereby the capacitor of said other transistor capacitor series can be charged switching means for discharging said capacitors.
Claim 12
Dependent Claim
174 words
A circuit for generating timing edges within a clock cycle comprising: clock means, means for generating a controlled current, and a ratio circuit coupled to an output, said clock means and said generating means, said ratio circuit comprising; at least two capacitors and two transistors, each of said transistors having a control electrode, each of said capacitors being coupled in series with a respective transistor to form a respective capacitor transistor series, each one of said capacitor transistor series being coupled in parallel between said controlled current generating means and ground, said clock means being directly coupled to the control electrode of the transistor of one of said capacitor transistor series whereby the capacitor to said one of said capacitor transistor series can be charged, means coupled to the control electrode of the transistor in the other of said capacitor transistor series for selectively turning off the transistor in the other of said capacitor transistor series, whereby the capacitor of said other transistor capacitor series can be charged switching means for discharging said capacitors.
References Cited (Backward Citations)
US4037162A
Cited
US4914319A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1995-03-03 | 1995-09-02 | 1996-03-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-03 | 1999-09-02 | 2000-03-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-03 | 2003-09-02 | 2004-03-03 | $7700.00 | Window Closed / Lapsed |