US5092032A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Manufacturing method for a multilayer printed circuit board
Assignee: International Business Machines Corp
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Filing: 1991-05-15
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Granted: 1992-03-03
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Expires: 2011-05-15
Abstract
Abstract Disclosed is a method for manufacturing a multilayer circuit board in which landless inter-layer connection is made between a lower-layer electric circuit and an upper-layer electric circuit formed on a substrate. The method of the invention utilizes a single photoresist to form a circuitization layer and the conductive via extending upwardly from it. In the method of the invention a metal layer is applied to the substrate, and photoresist is applied to the metal layer. The photoresist is then exposed and developed to define a resist hole. A via bump is formed in the resist hole. The residual resist is then imaged to form a first circuit pattern in the underlying metal layer. The remaining photoresist is removed from the first metal layer, and an organic dielectric layer is formed on the etched metal layer, the exposed substrate, and via bump. The organic dielectric layer is then flattened or otherwise processed to expose the surface of the via bump. Either a second metal layer or an electronic part is deposited or applied to the exposed top surface of the via bump as an upper-layer electric circuit element.
Inventors
- 👤 Takahiro Murakami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 12:04
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/22; H05K3/24; H05K3/243; H05K3/46; H05K3/4644; H05K3/4647; H05K2201/00; H05K2201/03; H05K2201/0332; H05K2201/0335; H05K2201/0347; H05K2201/0364; H05K2201/0367; H05K2203/00; H05K2203/05; H05K2203/0502; H05K2203/0505; H05K2203/07; H05K2203/0703; H05K2203/0733; H05K3/02; H05K3/06; H05K3/061; H05K3/064; H10; H10W; H10W72/00; H10W72/071; H10W72/072; H10W72/20; H10W72/241; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49126; Y10T29/4913; Y10T29/49155; Y10T29/49156
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
190 words
A method for manufacturing a multilayer circuit board in which inter-layer connection is made between a lower-layer electric circuit and an upper-layer electric circuit formed on a substrate, comprising steps of: (a) applying a metal layer on said substrate, (b) applying a photoresist on said metal layer, (c) exposing and developing said photoresist to define a resist hole, (d) exposing the residual photoresist after said exposure and development to define a first circuit pattern, (e) forming a via bump in said resist hole, (f) developing said exposed residual photoresist, (g) etching the metal layer exposed by the development of said residual photoresist to form a first circuit pattern in said metal layer, (h) removing the remaining photoresist from the first metal layer, (i) forming an organic dielectric layer on the etched metal layer, the substrate exposed by etching, and on the via bump, (j) flattening the surface of said organic dielectric layer to expose the surface of said via bump, and (k) depositing a second metal layer or an electronic part for forming an upper-layer electric circuit on the exposed surface of said organic dielectric layer and said via bump.
Claim 2
Independent Claim
190 words
A method for manufacturing a multilayer circuit board in which inter-layer connection is made between a lower-layer electric circuit and an upper-layer electric circuit formed on a substrate, comprising steps of: (a) applying a metal layer on said substrate, (b) applying a photoresist on said metal layer, (c) exposing and developing said photoresist to define a resist hole, (d) exposing the residual photoresist after said exposure and development to define a first circuit pattern, (e) forming a via bump in said resist hole, (f) developing said exposed residual photoresist, (g) etching the metal layer exposed by the development of said residual photoresist to form a first circuit pattern in said metal layer, (h) removing the remaining photoresist from the first metal layer, (i) forming an organic dielectric layer on the etched metal layer, the substrate exposed by etching, and on the via bump, (j) flattening the surface of said organic dielectric layer to expose the surface of said via bump, and (k) depositing a second metal layer or an electronic part for forming an upper-layer electric circuit on the exposed surface of said organic dielectric layer and said via bump.
Claim 3
Independent Claim
48 words
The method of claim (1) for manufacturing a multilayer circuit board, wherein said via bump consists of the same material as said first metal layer, and a protective film consisting of a material different from said material is formed on the upper portion of the plating via bump.
Claim 4
Independent Claim
18 words
The method of claim (1) for manufacturing a multilayer circuit board, wherein said photoresist is a positive photoresist.
Claim 5
Independent Claim
179 words
A method for manufacturing a multilayer circuit board, in which inter-layer connection is made between a lower-layer electric circuit and an upper-layer electric circuit formed on a substrate, comprising steps of: (a) forming a metal layer on said substrate, (b) coating a photoresist on said metal layer, (c) exposing and developing said photoresist to define a resist hole, (d) forming a via bump in said resist hole, (e) exposing and developing the residual photoresist after said exposure and development to define a first electric circuit pattern, (f) etching the metal layer exposed through the development of said photoresist to form said first electric circuit, (g) removing the photoresist from the metal layer constituting the first electric circuit, (h) coating an organic dielectric layer on the circuitized first metal layer etched, the substrate exposed by etching, and the via bump, (i) flattening the surface of said organic dielectric layer to expose the surface of said via bump, and (j) depositing another metal layer or electronic part on the exposed surface of said organic dielectric layer and said plating via bump.
Claim 6
Independent Claim
179 words
A method for manufacturing a multilayer circuit board, in which inter-layer connection is made between a lower-layer electric circuit and an upper-layer electric circuit formed on a substrate, comprising steps of: (a) forming a metal layer on said substrate, (b) coating a photoresist on said metal layer, (c) exposing and developing said photoresist to define a resist hole, (d) forming a via bump in said resist hole, (e) exposing and developing the residual photoresist after said exposure and development to define a first electric circuit pattern, (f) etching the metal layer exposed through the development of said photoresist to form said first electric circuit, (g) removing the photoresist from the metal layer constituting the first electric circuit, (h) coating an organic dielectric layer on the circuitized first metal layer etched, the substrate exposed by etching, and the via bump, (i) flattening the surface of said organic dielectric layer to expose the surface of said via bump, and (j) depositing another metal layer or electronic part on the exposed surface of said organic dielectric layer and said plating via bump.
Claim 7
Independent Claim
50 words
The method of claim (4) for manufacturing a multilayer wiring board, wherein said via bump plating via bump consists of the same material as said metal layer, and a protective film consisting of a material different from said material is formed in the upper portion of the plating via bump.
Claim 8
Independent Claim
18 words
The method of claim (4) for manufacturing a multilayer circuit board, wherein said photoresist is a positive photoresist.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-03 | 1995-09-02 | 1996-03-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-03 | 1999-09-02 | 2000-03-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-03 | 2003-09-02 | 2004-03-03 | $7700.00 | Window Closed / Lapsed |