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US5091887A
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Dynamic semiconductor memory device
Assignee: Mitsubishi Electric Corp
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Filing: 1990-05-11
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Granted: 1992-02-25
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Expires: 2010-05-11
Abstract
Abstract A dynamic semiconductor memory device includes a memory cell array comprising a plurality of word lines (WL 0 -WL n ), a plurality of bit lines (BL n -BL n+11 ) and a plurality of memory cells (MC) connected to intersections between the word lines and the bit lines. The plurality of bit lines include bit line pairs of two bit lines, one being a bit line for reading information of a memory cell, and the other being a bit line for providing a reference potential, and sense amplifiers (SA1-SA5) for detecting a potential difference between each bit line pair to amplify the same. The plurality of bit line pairs include bit line pairs crossing with each other such that a capacitance is balanced between adjacent bit lines, and bit line pairs having no crossing portion between which the bit line pairs crossing with each other are arranged such that a capacitance is balanced between said adjacent bit lines. Accordingly, the bit lines having the crossing portions receive the same noise from the other adjacent bit lines, and the bit lines having no crossing portion receive no noise between the paired bit lines, so that a reading potential difference can be reduced.
Inventors
- 👤 Mikio Asakura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 14:08
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/18; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4097
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
165 words
A dynamic semiconductor memory device comprising: a memory cell array including a plurality of word lines, a plurality of bit lines and a plurality of memory cells (MC) connected to the intersections between the word lines and the bit lines, said plurality of bit lines comprising bit line pairs each including a bit line for reading information of said memory cell and a bit line for providing a reference potential, sense amplifiers for detecting and amplifying a potential difference between the bit lines in each bit line pair, said plurality of bit line pairs comprising: a first bit line pair having bit lines crossing with each other such that a capacitance is balanced between adjacent bit lines, and a second bit line pair having bit lines arranged approximately parallel to each other, said bit lines of said second bit line pair having said first bit line pair therebetween, said first bit line pair being arranged between the bit lines of said second bit line pair.
Claim 2
Dependent Claim
165 words
A dynamic semiconductor memory device comprising: a memory cell array including a plurality of word lines, a plurality of bit lines and a plurality of memory cells (MC) connected to the intersections between the word lines and the bit lines, said plurality of bit lines comprising bit line pairs each including a bit line for reading information of said memory cell and a bit line for providing a reference potential, sense amplifiers for detecting and amplifying a potential difference between the bit lines in each bit line pair, said plurality of bit line pairs comprising: a first bit line pair having bit lines crossing with each other such that a capacitance is balanced between adjacent bit lines, and a second bit line pair having bit lines arranged approximately parallel to each other, said bit lines of said second bit line pair having said first bit line pair therebetween, said first bit line pair being arranged between the bit lines of said second bit line pair.
Claim 3
Dependent Claim
44 words
A dynamic semiconductor memory device according to claim 1, wherein bit lines adjacent to a bit line of said second bit line pair, comprises at least one bit line of said second bit line pair and a third bit line pair having crossing portions.
Claim 4
Dependent Claim
25 words
A dynamic semiconductor memory device according to claim 2, wherein bit line pairs arranged at opposite ends of the memory cell array comprise crossing portions.
Claim 5
Dependent Claim
42 words
A dynamic semiconductor device according to claim 1, wherein bit line pairs arranged at opposite ends of the memory cell array and adjacent to portions of the word lines having a lining of conductive material thereon comprise bit lines having crossing portions.
Claim 6
Dependent Claim
36 words
A dynamic semiconductor memory device according to claim 1, wherein each bit line pair of said first bit line pair is arranged between bit lines of a bit line pair of said second bit line pair.
Claim 7
Dependent Claim
64 words
A dynamic semiconductor memory device according to claim 1, wherein a bit line pair of said first bit line pair is arranged between bit lines of adjacent pairs of bit lines of said second bit line pair, and another bit line pair of said first bit line pair is arranged between bit lines of a bit line pair of said second bit line pair.
Claim 8
Dependent Claim
40 words
A dynamic semiconductor memory device according to claim 1, wherein said bit line pairs are grouped into groups containing two bit line pairs of said first bit line pair and one bit line pair of said second bit line pair.
Claim 9
Dependent Claim
42 words
A dynamic semiconductor memory device according to claim 1, wherein one bit line pair of said first bit line pair is arranged adjacent to a portion of said word lines in which said word lines are lined with a highly conductive material.
Claim 10
Dependent Claim
109 words
A dynamic semiconductor memory device having memory cells arranged in a matrix at intersections of word lines and bit lines and wherein said bit lines are arranged in pairs of said bit lines, the improvement comprising: said bit line pairs being of a first type having at least one portion in which the bit lines intersect with each other and a second type having bit lines arranged approximately parallel to each other, at least one said bit line pair of said first type being separated from another bit line pair of said first type by at least one bit line of a bit line pair of said second type.
Claim 11
Dependent Claim
109 words
A dynamic semiconductor memory device having memory cells arranged in a matrix at intersections of word lines and bit lines and wherein said bit lines are arranged in pairs of said bit lines, the improvement comprising: said bit line pairs being of a first type having at least one portion in which the bit lines intersect with each other and a second type having bit lines arranged approximately parallel to each other, at least one said bit line pair of said first type being separated from another bit line pair of said first type by at least one bit line of a bit line pair of said second type.
Claim 12
Dependent Claim
102 words
A dynamic semiconductor memory device having memory cells arranged in a matrix at intersections of word lines and bit lines and wherein said bit lines are arranged in pairs of said bit lines, the improvement comprising: said bit line pairs being of a first type having at least one portion in which the bit lines intersect with each other and a second type of bit line pair having bit lines arranged approximately parallel to each other, at least one bit line of a pair of bit lines of said second type being adjacent to a bit line pair of said first type.
Claim 13
Dependent Claim
102 words
A dynamic semiconductor memory device having memory cells arranged in a matrix at intersections of word lines and bit lines and wherein said bit lines are arranged in pairs of said bit lines, the improvement comprising: said bit line pairs being of a first type having at least one portion in which the bit lines intersect with each other and a second type of bit line pair having bit lines arranged approximately parallel to each other, at least one bit line of a pair of bit lines of said second type being adjacent to a bit line pair of said first type.
Claim 14
Dependent Claim
35 words
A dynamic semiconductor memory device according to claim 10, wherein said bit lines of a bit line pair of said second type are separated from each other by bit line pairs of said first type.
Claim 15
Dependent Claim
35 words
A dynamic semiconductor memory device according to claim 10, wherein crossing portions of said first type of bit line pair are separated from each other by one half a length of said bit line pair.
References Cited (Backward Citations)
US3942164A
Cited
US5001669A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-02-24 | 1995-08-26 | 1996-02-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-02-24 | 1999-08-26 | 2000-02-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-02-24 | 2003-08-26 | 2004-02-25 | $7700.00 | Window Closed / Lapsed |