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US5091882A
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Nonvolatile semiconductor memory device and method of operating the same
Assignee: Toshiba Corp
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Filing: 1990-07-30
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Granted: 1992-02-25
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Expires: 2010-07-30
Abstract
Abstract In a nonvolatile semiconductor memory device such as EEPROMs which comprises a semiconductor substrate of one conductivity type having source and drain regions of opposite conductivity type for defining a channel region therebetween, and a stacked gate including a gate insulating film, a floating gate and a control gate provided through an interlevel insulator above the floating gate, an erase gate having an electrode is provided above the channel region through an insulating film which is contiguous to the gate insulating film. The erase gate is also insulated from the stacked gate through a side wall insulating film. For removing a charge carrier stored in the floating gate, a high voltage is applied to the erase gate, while grounding the source and drain regions and the control gate, respectively.
Inventors
- 👤 Kiyomi Naruke
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:25
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
128 words
A nonvolatile semiconductor memory device comprising: a semiconductor substrate of one conductivity type having source and drain regions of opposite conductivity type for defining a channel region therebetween; a stacked gate provided on said channel region, said stacked gate including a gate insulating film overlapping said drain region, a floating gate disposed on said gate insulating film and a control gate provided through an interlevel insulator above said floating gate, an erase gate provided above said channel region through an insulating film contiguous to said gate insulating film, said insulating film overlapping said source region, said erase gate being insulated from said stacked gate through a side wall insulating film, and an electrode provided on said source and drain regions, said control gate and said erase gate, respectively.
Claim 2
Dependent Claim
128 words
A nonvolatile semiconductor memory device comprising: a semiconductor substrate of one conductivity type having source and drain regions of opposite conductivity type for defining a channel region therebetween; a stacked gate provided on said channel region, said stacked gate including a gate insulating film overlapping said drain region, a floating gate disposed on said gate insulating film and a control gate provided through an interlevel insulator above said floating gate, an erase gate provided above said channel region through an insulating film contiguous to said gate insulating film, said insulating film overlapping said source region, said erase gate being insulated from said stacked gate through a side wall insulating film, and an electrode provided on said source and drain regions, said control gate and said erase gate, respectively.
Claim 3
Dependent Claim
24 words
A nonvolatile semiconductor memory device according to claim 1, wherein a thickness of said gate insulating film is of the order of 100 Å.
Claim 4
Dependent Claim
25 words
A nonvolatile semiconductor memory device according to claim 1, wherein a thickness of said side wall insulating film is of the order of 800 Å.
Claim 5
Dependent Claim
26 words
A nonvolatile semiconductor memory device according to claim 1, wherein a comparatively low impurity concentration region of opposite conductivity type is provided underneath said drain region.
Claim 6
Dependent Claim
18 words
A nonvolatile semiconductor memory device according to claim 1, wherein said channel region has a controlled threshold voltage.
Claim 7
Dependent Claim
29 words
A nonvolatile semiconductor memory device according to claim 1, wherein said interlevel insulator is comprised of a silicon oxide film, a silicon nitride film and a silicon oxide film.
Claim 8
Dependent Claim
165 words
A nonvolatile semiconductor memory device comprising: a semiconductor substrate of one conductivity type having source and drain regions of opposite conductivity type for defining a channel region therebetween; a stacked gate provided on said channel region, said stacked gate including a gate insulating film overlapping said drain region, a floating gate disposed on said gate insulating film and a control gate provided through an interlevel insulator above said floating gate, a select gate provided above said channel region through an insulating film contiguous to said gate insulating film, said insulating film overlapping said source region, said select gate being insulated from said stacked gate through one side wall insulating film, an erase gate provided above said drain region through an insulating film contiguous to said gate insulating film, said erase gate being insulated from said stacked gate through the other side wall insulating film, and an electrode provided on said source and drain regions, said control gate, said select gate and said erase gate, respectively.
Claim 9
Dependent Claim
165 words
A nonvolatile semiconductor memory device comprising: a semiconductor substrate of one conductivity type having source and drain regions of opposite conductivity type for defining a channel region therebetween; a stacked gate provided on said channel region, said stacked gate including a gate insulating film overlapping said drain region, a floating gate disposed on said gate insulating film and a control gate provided through an interlevel insulator above said floating gate, a select gate provided above said channel region through an insulating film contiguous to said gate insulating film, said insulating film overlapping said source region, said select gate being insulated from said stacked gate through one side wall insulating film, an erase gate provided above said drain region through an insulating film contiguous to said gate insulating film, said erase gate being insulated from said stacked gate through the other side wall insulating film, and an electrode provided on said source and drain regions, said control gate, said select gate and said erase gate, respectively.
Claim 10
Dependent Claim
24 words
A nonvolatile semiconductor memory device according to claim 7, wherein a thickness of said gate insulating film is of the order of 100 Å.
Claim 11
Dependent Claim
27 words
A nonvolatile semiconductor memory device according to claim 7, wherein a thickness of each of said side wall insulating film is of the order of 800 Å.
Claim 12
Dependent Claim
18 words
A nonvolatile semiconductor memory device according to claim 7, wherein said channel region has a controlled threshold voltage.
Claim 13
Dependent Claim
28 words
A nonvolatile semiconductor memory device according to claim 7, wherein said interlevel insulator is comprised of a silicon oxide film, silicon nitride film and a silicon oxide film.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1995-02-24 | 1995-08-26 | 1996-02-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-02-24 | 1999-08-26 | 2000-02-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-02-24 | 2003-08-26 | 2004-02-25 | $7700.00 | Window Closed / Lapsed |