US5091872A
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Apparatus and method for performing spike analysis in a logic simulator
Assignee: Nokia Bell Labs
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Filing: 1989-06-23
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Granted: 1992-02-25
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Expires: 2009-06-23
Abstract
Abstract A logic circuit simulator for detecting a spike condition at the output of a simulated gate. A plurality of autonomous devices are arranged for parallel pipeline operation. Each device is designed to perform only a part of the overall simulation function. One of the devices is responsive to signals representing gate input stimuli and to gate propagation delay data primarily for performing the spike analysis function. Another device performs the function of gate output signal scheduling in response to gate input stimuli for transmitting messages containing said signals to the spike analyzing device and other devices of the simulator. When the spike analyzing device detects a spike condition, it transmits into the pipeline signals indicating the scheduling of an unknown output event on the gate in question.
Inventors
- 👤 Prathima Agrawal
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 19:36
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
223 words
A logic circuit simulator arranged for detecting spike conditions at the outputs of gates in a simulated logic network, which comprises means for generating input messages specifying the scheduled times of output events and resulting new output values for said gates; first and second time wheels each having a plurality of time slots corresponding to specific times, scheduling means responsive to said input messages for linking the identities and last-received new output values for gates having output events scheduled at a specific time to the time slot in said first time wheel corresponding to such time and for transmitting output messages indicating new output values for the gates linked to each particular time slot in said first time wheel at the time associated with that particular time slot; and analyzing means responsive to said input messages for determining the elapsed time between arrivals of successive input messages for each gate and, if said elapsed time exceeds a reference time for said gate, linking the identity of said gate and the presence of a spike condition with the time slot of said second time wheel corresponding to the start of the spike condition and for transmitting output messages indicating spike conditions for the gates linked to each particular time slot in said second time wheel at the time associated with that particular time slot.
Claim 2
Dependent Claim
223 words
A logic circuit simulator arranged for detecting spike conditions at the outputs of gates in a simulated logic network, which comprises means for generating input messages specifying the scheduled times of output events and resulting new output values for said gates; first and second time wheels each having a plurality of time slots corresponding to specific times, scheduling means responsive to said input messages for linking the identities and last-received new output values for gates having output events scheduled at a specific time to the time slot in said first time wheel corresponding to such time and for transmitting output messages indicating new output values for the gates linked to each particular time slot in said first time wheel at the time associated with that particular time slot; and analyzing means responsive to said input messages for determining the elapsed time between arrivals of successive input messages for each gate and, if said elapsed time exceeds a reference time for said gate, linking the identity of said gate and the presence of a spike condition with the time slot of said second time wheel corresponding to the start of the spike condition and for transmitting output messages indicating spike conditions for the gates linked to each particular time slot in said second time wheel at the time associated with that particular time slot.
Claim 3
Dependent Claim
27 words
The simulator of claim 1 wherein said reference time is a first duration for a falling output value and a second duration for a rising output value.
Claim 4
Dependent Claim
15 words
The simulator of claim 1 wherein said reference time can be weighted by a variable.
Claim 5
Dependent Claim
31 words
The simulator of claim 1 wherein said analyzing means includes means for using the scheduled time for the next-to-last output event for said gate as the start of the spike condition.
Claim 6
Dependent Claim
51 words
The simulator of claim 1 wherein said first time wheel and said scheduling means are a first programmable processor and said second time wheel and said analyzing means are a second programmable processor, said first and second programmable processors being programmed to perform their respective portions of the overall circuit simulation.
Claim 7
Dependent Claim
27 words
The simulator of claim 5 wherein said means for generating input messages, said first programmable processor and said second programmable processor are arranged in a series-connected pipeline.
Claim 8
Independent Claim
211 words
A method of detecting spike conditions at the outputs of gates in a simulated logic network, which comprises the steps of generating input messages specifying the scheduled times of output events and resulting new output values for said gates; maintaining first and second time wheels, each time wheel having a plurality of time slots corresponding to specific times; responsive to said input messages, linking the identities and last-received new output values of gates having output events scheduled at a specific time with the time slot of said first time wheel corresponding to such time; at the time associated with each time slot in said first time wheel, transmitting output messages indicating the new output values for the gates linked to such time slot; analyzing said input messages by determining the elapsed time between arrivals of successive input messages for each gate and, if said elapsed time exceeds a reference time for said gate, linking the identity of said gate and the presence of a spike condition with the time slot of said second time wheel corresponding to the start of said spike condition; and at the time associated with each time slot in said second time wheel, transmitting output messages indicating spike conditions for the gates linked to such time slot.
Claim 9
Independent Claim
211 words
A method of detecting spike conditions at the outputs of gates in a simulated logic network, which comprises the steps of generating input messages specifying the scheduled times of output events and resulting new output values for said gates; maintaining first and second time wheels, each time wheel having a plurality of time slots corresponding to specific times; responsive to said input messages, linking the identities and last-received new output values of gates having output events scheduled at a specific time with the time slot of said first time wheel corresponding to such time; at the time associated with each time slot in said first time wheel, transmitting output messages indicating the new output values for the gates linked to such time slot; analyzing said input messages by determining the elapsed time between arrivals of successive input messages for each gate and, if said elapsed time exceeds a reference time for said gate, linking the identity of said gate and the presence of a spike condition with the time slot of said second time wheel corresponding to the start of said spike condition; and at the time associated with each time slot in said second time wheel, transmitting output messages indicating spike conditions for the gates linked to such time slot.
Claim 10
Dependent Claim
14 words
The method of claim 7 wherein the reference time is weighted by a variable.
Claim 11
Dependent Claim
27 words
The method of claim 7 wherein said reference time is a first duration for a falling output value and a second duration for a rising output value.
Claim 12
Dependent Claim
46 words
The method of claim 7 wherein said analyzing step further comprises linking the identity of said gate and the presence of a spike condition with the time slot of said second time wheel corresponding to the scheduled time for the next-to-last-received output event for said gate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-02-24 | 1995-08-26 | 1996-02-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-02-24 | 1999-08-26 | 2000-02-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-02-24 | 2003-08-26 | 2004-02-25 | $7700.00 | Window Closed / Lapsed |