Procedure for the control of frequency converter and rectifier/inverter bridges, and a modulator unit designed for implementing the procedure

Claim 2

A process for pulse-width modulation control of solid-state switches, used in three-phase frequency converter and rectifier/inverter bridges, each of said solid state switches having a reverse polarity component connected in inverse-parallel therewith, said process comprising the steps of: (a) producing two derived reference signals each of which has a first half consisting of the 0°-60° interval, and a second half consisting of the 120°-180° interval, of a cycle of a sinusoidal modulation reference signal, said derived reference signals having a cycle length of 120° and being displaced by 60° relative to each other; (b) obtaining modulation pulses for each phase by comparing said two derived reference signals, derived from modulation reference signals, to at least two out-of-phase triangular waveform type carrier signals; and (c) switching the solid state switches to be controlled at 60° intervals.

Claim 3

A process as defined in claim 1, wherein the number of said derived reference signals is the same as the number of said carrier signals.

Claim 4

A process for pulse-width modulation control of solid-state switches, used in three-phase frequency converter and rectifier/inverter bridges, each of said solid state switches having a reverse polarity component connected in inverse-parallel therewith, said process comprising the steps of: (a) producing two derived reference signals each of which has a first half consisting of the 0°-60° interval, and a second half consisting of the 120°-180° interval, of a cycle length of a sinusoidal modulation reference signal, said derived reference signals having a cycle length of 120° and being displaced by 60° relative to each other; (b) obtaining modulation pulses for each phase by comparing said two derived reference signals, derived from modulation reference signals, to at least two out-of-phase triangular waveform type carrier signals; (c) switching the solid state switches to be controlled at 60° intervals; and (d) implementing a zero-diode function by applying a continuous control signal in place of said modulation pulses to each solid state switch during a middle 60° interval of each cycle of said modulation pulses, while said reverse polarity component is turned on.

Claim 5

A process for pulse-width modulation control of solid-state switches, used in three-phase frequency converter and rectifier/inverter bridges, each of said solid state switches having a reverse polarity component connected in inverse-parallel therewith, said process comprising the steps of: (a) producing two derived reference signals each of which has a first half consisting of the 0°-60° interval, and a second half consisting of the 120°-180° interval, of a cycle length of a sinusoidal modulation reference signal, said derived reference signals having a cycle length of 120° and being displaced by 60° relative to each other; (b) obtaining modulation pulses for each phase by comparing said two derived reference signals, derived from modulation reference signals, to at least two out-of-phase triangular waveform type carrier signals; (c) switching the solid state switches to be controlled at 60° intervals; and (d) implementing a zero-diode function by applying a continuous control signal in place of said modulation pulses to each solid state switch during a middle 60° interval of each cycle of said modulation pulses, while said reverse polarity component is turned on.

Claim 6

A process as claimed in claim 3, further comprising the step of alternating a zero-diode function among the three phases in a rotary fashion.

Claim 7

A modulator unit for controlling with pulse width modulation solid-state switches used in three-phase frequency converter and rectifier/inverter bridges, each of said solid state switches having a reverse polarity component connected in inverse-parallel therewith, said unit comprising: at least a first memory circuit for storing modulation reference signals in a digital form; at least two D/A converters for converting an output of said memory circuit to an analog signal; at least two comparators each generating a pattern of modulation pulses by comparing said modulation reference signals to at least two out-of-phase triangular waveform type signals; an output decoder circuit for producing the modulation pulses for each phase from said pattern of modulation pulses; and an oscillator for generating said two out-of-phase triangular waveform type signals.

Claim 8

A modulator unit for controlling with pulse width modulation solid-state switches used in three-phase frequency converter and rectifier/inverter bridges, each of said solid state switches having a reverse polarity component connected in inverse-parallel therewith, said unit comprising: at least a first memory circuit for storing modulation reference signals in a digital form; at least two D/A converters for converting an output of said memory circuit to an analog signal; at least two comparators each generating a pattern of modulation pulses by comparing said modulation reference signals to at least two out-of-phase triangular waveform type signals; an output decoder circuit for producing the modulation pulses for each phase from said pattern of modulation pulses; and an oscillator for generating said two out-of-phase triangular waveform type signals.

Claim 9

A modulator unit as claimed in claim 5, further comprising a plurality of multiplying converters for adjusting the amplitude of said modulation reference signals.

Claim 10

A modulator unit as claimed in claim 5, further comprising: six-divider means for dividing said sinusoidal modulator reference signal 360° cycle into six equal intervals, wherein the least-significant bit of an output of said divider means represents the most-significant bit of an address of said stored modulation reference signals in said memory circuit; an N-divider means which provides the remaining bits of said address and whose ratio of division is selected to give a desired rate of reading of a stored modulation reference signal; and a voltage-controlled oscillator circuit for determining a basic rate at which said stored modulation reference signal is read.

Claim 11

A modulator unit as claimed in claim 5, further comprising a plurality of up/down-counting divider means whose direction of operation is selectable to allow selection of the direction in which said stored modulation reference signals are read.

Claim 12

A modulator unit as claimed in claim 5, further comprising a phase-locked loop circuit means for enabling said modulation reference signals to be synchronized with the mains phase voltage by applying at an input of said phase-locked loop means a mains phase voltage and the most-significant bit of the output of said six-divider means, so that the output of said phase-locked loop circuit means changes the frequency of said oscillator in such manner that said two out-of-phase triangular waveform type signals vary in steps.

Claim 13

A modulator unit as claimed in claim 5, wherein said output decoder circuit comprises a second memory storing said modulation pulses for each phase and control signals for solid state switches, wherein a first and a second control signal and said patterns of modulation pulses each represent an address bit and are directly used for addressing said memory for reading said control signals for solid state switches.

Claim 14

A modulator unit as claimed in claim 5, wherein said output decoder circuit comprises: a first and a second multiplexer for processing said pattern of modulation pulses; a third multiplexer for superposing a first control signal in the intervals when zero-diode function is required; a fourth multiplexer for generating modulated pulse trains for the intervals where zero-diode function is required; two-way switches for directing said pulse trains to the multiplexers by selecting either a rectifying or an inverting function according to a second control signal; and OR gate means for processing output signals provided by said first, second, third and fourth multiplexers to obtain said control signals for said solid state switches.