Patent US5091340A successfully refreshed from Google Patents.
US5091340A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for forming multilayer wirings on a semiconductor device
Assignee: NEC Corp
•
Filing: 1991-01-02
•
Granted: 1992-02-25
•
Expires: 2011-01-02
Abstract
Abstract A wiring method for semiconductor device includes the steps of forming a first seat in a portion where a lower wiring layer and an upper wiring layer are to be connected on a semiconductor substrate provided with semiconductor elements, forming a first conductor composed of an Al or Al-Cu alloy on the whole surface of the semiconductor substrate; forming the lower wiring layer by selectively removing the first conductor simultaneously with the formation of a second seat composed of the first conductor on the first seat; forming by the coating method a glass or organic silicon compound film as an interlevel insulating film, forming a through-hole by photoetching in the portion where the upper and lower wiring layers are to be connected; and forming a second conductor in order to form the upper wiring layer by photoetching.
Inventors
- 👤 Kazuyuki Mizushima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 09:46
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/063; H10W20/40; H10W20/41; H10W20/42
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
167 words
A method for forming multilayer wirings on a semiconductor device, comprising steps of forming a first seat formed of a first conductor in a portion where a lower wiring layer and an upper wiring layer on a semiconductor substrate are to be connected; forming a second conductor on said semiconductor substrate and said first seat; forming said lower wiring layer formed of said second conductor by selectively removing said second conductor simultaneously with the formation of a second seat formed of said second conductor on said first seat; forming by a chemical vapor deposition method a first interlevel insulating film on said semiconductor substrate, on said second seat and on said lower wiring layer; forming by a coating method a second interlevel insulating film on said first interlevel insulating film; forming a hole exposing said second seat in said first and second interlevel insulating films; and forming the upper wiring layer to be connected to said second seat via said hole on said second interlevel insulating film.
Claim 2
Independent Claim
167 words
A method for forming multilayer wirings on a semiconductor device, comprising steps of forming a first seat formed of a first conductor in a portion where a lower wiring layer and an upper wiring layer on a semiconductor substrate are to be connected; forming a second conductor on said semiconductor substrate and said first seat; forming said lower wiring layer formed of said second conductor by selectively removing said second conductor simultaneously with the formation of a second seat formed of said second conductor on said first seat; forming by a chemical vapor deposition method a first interlevel insulating film on said semiconductor substrate, on said second seat and on said lower wiring layer; forming by a coating method a second interlevel insulating film on said first interlevel insulating film; forming a hole exposing said second seat in said first and second interlevel insulating films; and forming the upper wiring layer to be connected to said second seat via said hole on said second interlevel insulating film.
Claim 3
Dependent Claim
42 words
A method for forming multilayer wirings on a semiconductor device as claimed in claim 1, wherein said first interlevel insulating film is a silicon nitride film or silicon oxide film, said second interlevel insulating film being a glass or organic compound film.
Claim 4
Dependent Claim
28 words
A method for forming multilayer wirings on a semiconductor device as claimed in claim 1, wherein said first and second conductors are made of Al or Al--Cu alloy.
Claim 5
Independent Claim
187 words
A method for forming multilayer wirings on a semiconductor device, comprising steps of forming a first seat formed of a first conductor in a portion where a lower wiring layer and an upper wiring layer on a semiconductor substrate are to be connected; forming a second conductor on said semiconductor substrate and said first seat; forming said lower wiring layer formed of said second conductor by selectively removing said second conductor simultaneously with the formation of a second seat formed of a said second conductor on said first seat; forming by a chemical vapor deposition method a first interlevel insulating film on said semiconductor substrate on said second seat and on said lower wiring layer; forming by a coating method a second interlevel insulating film on said first interlevel insulating film; forming by a chemical vapor deposition method a third interlevel insulating film on said second interlevel insulating film; forming a hole exposing said second seat in said first, second and third interlevel insulating films; and forming the upper wiring layer to be connected to said second seat via said hole on said third interlevel insulating film.
Claim 6
Independent Claim
187 words
A method for forming multilayer wirings on a semiconductor device, comprising steps of forming a first seat formed of a first conductor in a portion where a lower wiring layer and an upper wiring layer on a semiconductor substrate are to be connected; forming a second conductor on said semiconductor substrate and said first seat; forming said lower wiring layer formed of said second conductor by selectively removing said second conductor simultaneously with the formation of a second seat formed of a said second conductor on said first seat; forming by a chemical vapor deposition method a first interlevel insulating film on said semiconductor substrate on said second seat and on said lower wiring layer; forming by a coating method a second interlevel insulating film on said first interlevel insulating film; forming by a chemical vapor deposition method a third interlevel insulating film on said second interlevel insulating film; forming a hole exposing said second seat in said first, second and third interlevel insulating films; and forming the upper wiring layer to be connected to said second seat via said hole on said third interlevel insulating film.
Claim 7
Dependent Claim
43 words
A method for forming multilayer wirings on a semiconductor device as claimed in claim 4, wherein said first and third interlevel insulating films are silicon nitride film or silicon oxide films, said second interlevel insulating film being a glass or organic compound film.
Claim 8
Dependent Claim
28 words
A method for forming multilayer wirings on a semiconductor device as claimed in claim 4, wherein said first and second conductors are made of Al or Al--Cu alloy.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-02-24 | 1995-08-26 | 1996-02-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-02-24 | 1999-08-26 | 2000-02-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-02-24 | 2003-08-26 | 2004-02-25 | $7700.00 | Window Closed / Lapsed |