Non-volatile memory cell

Claim 2

A non-volatile, static memory cell comprising: a magnetic patch for storing information in the form of a magnetic field; magnetizing means for writing said information to said patch; Hall effect sensor means for reading said information from said patch, said sensor means including a Hall bar; means for flowing a current through said Hall bar in the presence of said magnetic field to generate a Hall voltage across said Hall bar in a direction transverse to said magnetic field and said current; and wherein said Hall effect sensor means further includes a detector means coupled to said Hall bar for detecting said Hall voltage, said Hall voltage being representative of said information.

Claim 3

The memory cell of claim 1 wherein said Hall bar comprises an inversion layer produced by a metal-oxide-semiconductor (MOS) device.

Claim 4

The memory cell of claim 2 wherein said detector means comprises of a pair of bipolar junction transistors fabricated in a semiconductor substrate, said transistors having their bases coupled across opposite sides of said Hall bar.

Claim 5

The memory cell of claim 3 wherein said magnetic patch stores said information in the form of multiple magnetic domains.

Claim 6

The memory cell of claim 3 wherein said information is binary in nature.

Claim 7

The memory cell of claim 1 wherein said Hall bar comprises a two-dimensional electron gas.

Claim 8

A Hall effect semiconductor memory cell for storing information comprising: a magnetic patch disposed above the surface of a semiconductor substrate, said patch storing said information in the form of a magnetic field; means for writing said information to said patch; means for generating current flow in a first region of said semiconductor substrate in a direction transverse to said magnetic field, said current flow producing a Hall voltage across said first region; and sensor means coupled to said first region for sensing said Hall voltage, said sensor means including second and third substrate regions formed adjacent to said first region such that when Hall voltage is produced across said first region, said Hall voltage also appears across said second and third regions.

Claim 9

A Hall effect semiconductor memory cell for storing information comprising: a magnetic patch disposed above the surface of a semiconductor substrate, said patch storing said information in the form of a magnetic field; means for writing said information to said patch; means for generating current flow in a first region of said semiconductor substrate in a direction transverse to said magnetic field, said current flow producing a Hall voltage across said first region; and sensor means coupled to said first region for sensing said Hall voltage, said sensor means including second and third substrate regions formed adjacent to said first region such that when Hall voltage is produced across said first region, said Hall voltage also appears across said second and third regions.

Claim 10

The memory cell of claim 7 wherein a bit of said information corresponds to a single magnetic domain within said patch.

Claim 11

The memory cell of claim 7 wherein said first region comprises an inversion layer produced by a metal-oxide-semiconductor device.

Claim 12

The memory cell of claim 9 wherein said second and third regions comprise the bases of bipolar transistors, said bases being of the same conductivity type as said inversion layer.

Claim 13

The memory cell of claim 10 wherein bipolar transistors comprise NPN transistors.

Claim 14

The memory cell of claim 10 further comprising a circuit means for decoding of said Hall voltage, said circuit means being coupled to the emitters of said bipolar transistors.

Claim 15

The memory cell of claim 7 wherein said writing means comprises at least one pair of current carrying conductors formed around said patch, said conductors accommodating a writing current of sufficient magnitude to magnetize said patch.

Claim 16

A Hall effect memory cell fabricated on a semiconductor body of a first conductivity type comprising: spaced-apart first and second regions of a second conductivity type formed within said body, said first and second regions defining a third region therebetween; a gate member disposed above said third region and insulated from said body; fourth and fifth regions of said first conductivity type formed within said first and second regions, respectively; a magnetic patch disposed above said gate member for storing information in the form of a magnetic field; means for generating a current in said third region in a direction transverse to said magnetic field wherein application of a predetermined potential to said gate member creates an inversion layer beneath the surface of said body in said third region, a Hall voltage being produced in a direction transverse to said current and said magnetic field across said third region, said Hall voltage being coupled across said first and second regions through said inversion layer; and circuit means coupled to said fourth and fifth regions for detecting said Hall voltage to read said information.

Claim 17

A Hall effect memory cell fabricated on a semiconductor body of a first conductivity type comprising: spaced-apart first and second regions of a second conductivity type formed within said body, said first and second regions defining a third region therebetween; a gate member disposed above said third region and insulated from said body; fourth and fifth regions of said first conductivity type formed within said first and second regions, respectively; a magnetic patch disposed above said gate member for storing information in the form of a magnetic field; means for generating a current in said third region in a direction transverse to said magnetic field wherein application of a predetermined potential to said gate member creates an inversion layer beneath the surface of said body in said third region, a Hall voltage being produced in a direction transverse to said current and said magnetic field across said third region, said Hall voltage being coupled across said first and second regions through said inversion layer; and circuit means coupled to said fourth and fifth regions for detecting said Hall voltage to read said information.

Claim 18

The memory cell of claim 14 wherein said first conductivity type is n-type and said second conductivity type is p-type.

Claim 19

The memory cell of claim 15 wherein said circuit means comprises a pair of bipolar transistors in which said fourth and fifth regions comprise the emitter regions, said first and second regions comprise the base regions, and said body comprises the common collector region of said bipolar transistors.

Claim 20

The memory cell of claim 16 wherein said gate member comprises polysilicon.