Method for forming a germanium layer and a heterojunction bipolar transistor

Claim 2

A process for forming a P-germanium layer on a layer of silicon: depositing a first N-germanium silicon layer on the silicon layer; depositing a P-germanium silicon layer on the first N-germanium silicon layer; and heating the wafer in an oxidizing ambient until said P-germanium silicon layer transforms into the P-germanium layer under a layer of formed silicon dioxide.

Claim 3

The process of claim 1, wherein the deposition of the first N-germanium silicon layer is by chemical vapor deposition.

Claim 4

The process of claim 1, where the deposition of the P-germanium silicon layer is by chemical vapor deposition.

Claim 5

The process of claim 1, wherein the deposition of the first N-germanium silicon is expitaxial to the silicon substrate.

Claim 6

The process of claim 1, wherein the deposition of the P-germanium silicon is expitaxial to said N-germanium silicon.

Claim 7

The process of claim 1, wherein the thickness of said N-germanium silicon layer is such that the lattice is relaxed and free from stress due to the formation of dislocations at its interface with the silicon substrate.

Claim 8

The process of claim 1, wherein the P-germanium silicon is in compressive stress and commensurate with said N-germanium silicon layer.

Claim 9

The process of claim 1, wherein said heating step comprises the step of steam oxidizing the wafer to approximately 1000 degrees Centigrade.

Claim 10

A process for forming a germanium layer on a wafer, comprising the steps of: depositing a first layer of N-germanium silicon on said wafer; depositing a second layer of P-germanium silicon on said first layer of N-germanium silicon; and oxidizing the wafer until the second layer of P-germanium silicon forms a separate layer of P-germanium.

Claim 11

A process for forming a germanium layer on a wafer, comprising the steps of: depositing a first layer of N-germanium silicon on said wafer; depositing a second layer of P-germanium silicon on said first layer of N-germanium silicon; and oxidizing the wafer until the second layer of P-germanium silicon forms a separate layer of P-germanium.

Claim 12

The process of claim 9, wherein the step of depositing the second P-germanium silicon layer comprises the process of depositing the P-germanium silicon layer having a thickness of approximately 2300 angstroms.

Claim 13

The process of claim 10, wherein the forming of said P-germanium layer produces a layer having a thickness of approximately 750 angstroms.

Claim 14

The process of claim 9, further comprising the step of growing an N-germanium silicon layer on the wafer to approximately 1 micron before depositing said P-germanium silicon layer to the wafer.

Claim 15

The process of claim 9, further comprising the step of depositing tetraethylorthosilane (TEOS) to said P-germanium silicon layer to form an oxide layer.

Claim 16

The process of claim 13, further comprising the step of forming a photoresist pattern onto said oxide layer.

Claim 17

The process of claim 14, further comprising the step of implanting boron ions into the wafer.

Claim 18

The process of claim 15, further comprising the step of selectively stripping the photoresist from the wafer.

Claim 19

The process of claim 16, further comprising the step of implanting phosphorous dopant to create N+ isolation regions.

Claim 20

The process of claim 17, further comprising the step of stripping said TEOS layer from the wafer with hydrofluoric acid.

Claim 21

The process of claim 18, further comprising the step of growing an oxide film on said P-germanium silicon layer.

Claim 22

The process of claim 19, further comprising the step of exposing said P-germanium layer.

Claim 23

The process of claim 20, further comprising the step of depositing a first conducting layer to said exposed region.

Claim 24

The process of claim 21, further comprising the step of exposing the wafer having boron implanted therein.

Claim 25

The process of claim 22, further comprising the step of depositing a second conducting layer to said exposed wafer.

Claim 26

The process of claim 9, wherein the deposition of the first N-germanium silicon layer is by chemical vapor deposition.

Claim 27

The process of claim 9, wherein the deposition of the P-germanium silicon layer is by chemical vapor deposition.

Claim 28

The process of claim 9, wherein the deposition of the first N-germanium silicon is expitaxial to the wafer.

Claim 29

The process of claim 9, wherein the deposition of the P-germanium silicon is expitaxial to said N-germanium silicon.

Claim 30

The process of claim 9, wherein the thickness of said N-germanium silicon layer is such that the lattice is relaxed and free from stress due to the formation of dislocations at its interface with the wafer.

Claim 31

The process of claim 9, wherein the P-germanium silicon is in compressive stress and commensurate with said N-germanium silicon layer.

Claim 32

A process for forming a P-germanium base for use in a heterojunction bipolar transistor (HBT) on a wafer which comprises the steps of: forming an N-germanium silicon buffer layer onto a silicon N-substrate; depositing a first P-germanium silicon on said buffer layer; depositing an oxide layer on said P-germanium silicon layer; depositing a photoresist layer on said oxide layer; selectively implanting boron into said deposited layers to form P+ contacts; depositing a second photoresist layer; implanting phosphorous to form N+ contacts; selectively stripping said second photoresist and said oxide layer from said P-germanium silicon layer; heating the wafer by steam oxidation to approximately 1000 degrees Centigrade to cause said P-germanium silicon layer to form a P-germanium layer selectively isolated from said N-germanium silicon layer, said heating forms a silicon dioxide layer on said P-germanium layer; selectively depositing a third photoresist layer; etching the wafer to form an exposed region; depositing a conductive layer in said exposed region; selectively etching the wafer to expose said P+ region; depositing aluminum over the P+ region to form the transistor of the present invention.

Claim 33

A process for forming a P-germanium base for use in a heterojunction bipolar transistor (HBT) on a wafer which comprises the steps of: forming an N-germanium silicon buffer layer onto a silicon N-substrate; depositing a first P-germanium silicon on said buffer layer; depositing an oxide layer on said P-germanium silicon layer; depositing a photoresist layer on said oxide layer; selectively implanting boron into said deposited layers to form P+ contacts; depositing a second photoresist layer; implanting phosphorous to form N+ contacts; selectively stripping said second photoresist and said oxide layer from said P-germanium silicon layer; heating the wafer by steam oxidation to approximately 1000 degrees Centigrade to cause said P-germanium silicon layer to form a P-germanium layer selectively isolated from said N-germanium silicon layer, said heating forms a silicon dioxide layer on said P-germanium layer; selectively depositing a third photoresist layer; etching the wafer to form an exposed region; depositing a conductive layer in said exposed region; selectively etching the wafer to expose said P+ region; depositing aluminum over the P+ region to form the transistor of the present invention.