US5088065A
Expired / Lapsed
US
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Static type semiconductor memory
Assignee: Hitachi Ltd
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Filing: 1990-10-05
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Granted: 1992-02-11
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Expires: 2010-10-05
Abstract
Abstract Information read out from a memory cell of a static type semiconductor memory is subjected to multi-stage sense amplification in an initial stage sense amplifier, a post-stage sense amplifier and a main amplifier and then transmitted to the input of an output buffer circuit. Since an equalizing circuit is connected to the complementary inputs of each stage of the multi-stage sense amplifier, an inverse information read operation can be executed at high speed. Initially, the initial stage sense amplifier, the post-stage sense amplifier and the main amplifier are controlled to operate in high amplification gain conditions so as to execute high speed sense amplification and thereafter controlled to operate in such low power consumption conditions that the read-out information output obtained by the high speed sense amplification will not disappear.
Inventors
- 👤 Shoji Hanamura
- 👤 Masaaki Kubotera
- 👤 Katsuro Sasaki
- 👤 Takao Oono
- 👤 Kiyotsugu Ueda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:34
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/06; G11C7/062; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
262 words
A static type semiconductor memory comprising: (1) a plurality of memory arrays each of which includes a plurality of memory cells, a plurality of complementary data line pairs, a first complementary data bus line pair, a first switch connected between said plurality of complementary data line pairs and said first complementary data bus line pair, and a first amplifier responding to complementary signals on said first complementary data line pairs being connected to a selected group of said plurality of memory cells; (2) a second complementary data bus line pair; (3) a second switch connected between complementary outputs of said first amplifier and said second complementary data bus line pair; (4) a second amplifier responding to complementary signals on said complementary data bus line pair; and (5) a third amplifier generating an output signal in response to complementary outputs of said second amplifier means; wherein an operation of said first amplifier is controlled by a first control signal; wherein an operation of said second amplifier is controlled by a second control signal; wherein an address signal for accessing a selective one from among said plurality of memory cells is supplied to said static type semiconductor memory, and wherein levels of said first and second control signals are set to such values that said first and second amplifiers operate in high amplification gain conditions in response to a change of level of said address signal, and thereafter levels of said first and second control signals are set to such values that said first and second amplifiers operate in a low power consumption conditions.
Claim 2
Dependent Claim
262 words
A static type semiconductor memory comprising: (1) a plurality of memory arrays each of which includes a plurality of memory cells, a plurality of complementary data line pairs, a first complementary data bus line pair, a first switch connected between said plurality of complementary data line pairs and said first complementary data bus line pair, and a first amplifier responding to complementary signals on said first complementary data line pairs being connected to a selected group of said plurality of memory cells; (2) a second complementary data bus line pair; (3) a second switch connected between complementary outputs of said first amplifier and said second complementary data bus line pair; (4) a second amplifier responding to complementary signals on said complementary data bus line pair; and (5) a third amplifier generating an output signal in response to complementary outputs of said second amplifier means; wherein an operation of said first amplifier is controlled by a first control signal; wherein an operation of said second amplifier is controlled by a second control signal; wherein an address signal for accessing a selective one from among said plurality of memory cells is supplied to said static type semiconductor memory, and wherein levels of said first and second control signals are set to such values that said first and second amplifiers operate in high amplification gain conditions in response to a change of level of said address signal, and thereafter levels of said first and second control signals are set to such values that said first and second amplifiers operate in a low power consumption conditions.
Claim 3
Dependent Claim
98 words
A static type semiconductor memory according to claim 1, further comprising: an equalizer minimizing a level difference of complementary inputs of at least one of said first, second and third amplifiers in response to a third control signal; wherein a level of said third control signal is of a value that a level difference minimizing operation of said equalizer is executed in response to the change of level of said address signal, and thereafter said level of said third control signal is of a value that said level difference minimizing operation of said equalizer means is in effective.
Claim 4
Dependent Claim
53 words
A static type semiconductor memory according to claim 2, wherein levels of said first and second control signals are set such that, when said first and second amplifiers operate in the low power consumption conditions, information read out through said first and second amplifiers operating in the high amplification gain conditions is held.
Claim 5
Dependent Claim
44 words
A static type semiconductor memory according to claim 3, wherein, after said level difference minimizing operation of said equalizers is ineffective the operating conditions of said first and second amplifiers are switched from said high amplification gain conditions to said low power consumption conditions.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-02-10 | 1995-08-12 | 1996-02-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-02-10 | 1999-08-12 | 2000-02-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-02-10 | 2003-08-12 | 2004-02-11 | $7700.00 | Window Closed / Lapsed |