Two-modulus variable frequency-divider circuit

Claim 2

A two-modulus variable-frequency divider circuit and a subsequent frequency divider circuit with respectively different response times, comprising: a variable-frequency divider having an input for receiving a signal to be frequency divided and having a frequency dividing factor that can be selectively set to a particular one of at least two values in accordance with a frequency dividing factor setting signal; a divide by 2 N frequency-divider arrangement having an input for receiving a frequency divided output from said variable-frequency divider, said divide by 2 N frequency-divider arrangement comprising a number, N, of divide by 2 frequency dividers, where N is an integer; an output; a monitor for monitoring an output of at least one of said divide by 2 frequency dividers of said divide by 2 N frequency-divider arrangement, a monitor output from said monitor being fed back to said variable-frequency-divider as said frequency dividing factor setting signal; an output signal converting circuit connected between the output of said divide by 2 N frequency-divider arrangement and said output of said two-modulus variable-frequency divider circuit; said output signal converting circuit including means for selectively making effective inverting or non-inverting said output of said divide by 2 N frequency-divider arrangement; a subsequent frequency divider circuit having a slower response time than said two-modulus variable frequency divider circuit receiving an output of said output signal converting circuit; and said means for selectively inverting or non-inverting being settable at either of its conditions to make effective a one of a positive-going and a negative-going change in condition of said output of said divide by 2 N frequency-divider arrangement which provides a maximum time for said subsequent frequency dividing circuit to respond to said frequency divided output, whereby slower response components may be used in said subsequent frequency dividing circuit.

Claim 3

A two-modulus variable-frequency divider circuit and a subsequent frequency divider circuit with respectively different response times, comprising: a variable-frequency divider having an input for receiving a signal to be frequency divided and having a frequency dividing factor that can be selectively set to a particular one of at least two values in accordance with a frequency dividing factor setting signal; a divide by 2 N frequency-divider arrangement having an input for receiving a frequency divided output from said variable-frequency divider, said divide by 2 N frequency-divider arrangement comprising a number, N, of divide by 2 frequency dividers, where N is an integer; an output; a monitor for monitoring an output of at least one of said divide by 2 frequency dividers of said divide by 2 N frequency-divider arrangement, a monitor output from said monitor being fed back to said variable-frequency divider as said frequency dividing factor setting signal; a signal converting circuit connected between said monitor and the output of the final one of those divide by 2 frequency dividers of said divide by 2 N frequency-divider arrangement which provides output to said monitor; said signal converting circuit including means for selectively inverting or non-inverting said frequency divided output from said final one of said divide by 2 frequency dividers in said divide by 2 N frequency-divider arrangement; and said means for selectively inverting or non-inverting being settable at either of its conditions to make effective a one of a positive-going and a negative-going change in condition of said output of said divide by 2 N frequency-divider arrangement so that a frequency divider circuit having relatively slow response time components is connected subsequent to said output of said two-modulus variable frequency divider circuit having relatively fast response time components can respond with a maximum response time to said one change in condition of said output of said divide by 2 N frequency divider arrangement.

Claim 4

A two-modulus variable-frequency divider circuit and a subsequent frequency divider circuit with respectively different response times, comprising: a variable-frequency divider having an input for receiving a signal to be frequency divided and having a frequency dividing factor that can be selectively set to a particular one of at least two values in accordance with a frequency dividing factor setting signal; a divide by 2 N frequency-divider arrangement having an input for receiving a frequency divided output from said variable-frequency divider, said divide by 2 N frequency-divider arrangement comprising a number, N, of divide by 2 frequency dividers, where N is an integer; an output; a monitor for monitoring an output of at least one of said divide by 2 frequency dividers of said divide by 2 N frequency-divider arrangement, a monitor output from said monitor being fed back to said variable-frequency divider as said frequency dividing factor setting signal; a signal converting circuit connected between said monitor and the output of the final one of those divide by 2 frequency dividers of said divide by 2 N frequency-divider arrangement which provides output to said monitor; said signal converting circuit including means for selectively inverting or non-inverting said frequency divided output from said final one of said divide by 2 frequency dividers in said divide by 2 N frequency-divider arrangement; and said means for selectively inverting or non-inverting being settable at either of its conditions to make effective a one of a positive-going and a negative-going change in condition of said output of said divide by 2 N frequency-divider arrangement so that a frequency divider circuit having relatively slow response time components is connected subsequent to said output of said two-modulus variable frequency divider circuit having relatively fast response time components can respond with a maximum response time to said one change in condition of said output of said divide by 2 N frequency divider arrangement.

Claim 5

A two-modulus variable-frequency divider circuit according to claim 1 or 2, wherein said means for selectively inverting includes means for permitting selection of one of its inverting and non-inverting conditions in response to a control signal externally applied thereto.

Claim 6

A two-modulus variable frequency-divider circuit according to claim 1 or 2, wherein said ÷2 N frequency-divider arrangement comprises two ÷2 frequency-dividers, and said monitor receives outputs from said two ÷2 frequency-dividers and a control signal applied from a circuit succeeding said two-modulus variable frequency-divider circuit to produce said monitor output.

Claim 7

A two-modulus variable frequency-divider circuit according to claim 3, wherein said ÷2 N frequency-divider arrangement comprises two ÷2 frequency-dividers, and said monitor receives outputs from said two ÷2 frequency-dividers and a control signal applied from a circuit succeeding said two-modulus variable frequency-divider circuit to produce said monitor output.

Claim 8

A two-modulus variable frequency-divider circuit according to claim 1, wherein the final stage ÷2 frequency-dividers of said ÷2 N frequency-divider arrangement includes a non-inverted output terminal and an inverted output terminal, and said signal converting circuit selectively couples said non-inverted and inverted output terminals to said output of said two-modulus variable frequency-divider circuit in accordance with a control signal externally applied thereto.

Claim 9

A two-modulus variable frequency-divider circuit comprising: a variable-frequency divider having an input for receiving a signal to be frequency divided and having a frequency dividing factor that can be selectively set to a particular one of at least two values in accordance with a frequency dividing factor setting signal; a divide by 2 N frequency-divider arrangement having an input for receiving a frequency divided output from said variable-frequency divider, said divide by 2 N frequency-divider arrangement comprising a number, N, of divide by 2 frequency dividers, where N is an integer; an output; a monitor for monitoring an output of at least one of said divide by 2 frequency dividers of said divide by 2 N frequency-divider arrangement, a monitor output from said monitor being fed back to said variable-frequency divider as said frequency dividing factor setting signal; a signal converting circuit connected between said monitor and the output of the final one of those divide by 2 frequency dividers of said divide by 2 N frequency-divider arrangement which provides output to said monitor; said signal converting circuit including means for selectively inverting or non-inverting said frequency divided output from said final one of said divide by 2 frequency dividers in said divide by 2 N frequency divider arrangement; and said means for selectively inverting or non-inverting being settable at either of its conditions to make effective a one of a positive-going and a negative-going change in condition of said output of said divide by 2 N frequency-divider arrangement so that a frequency divider circuit connected subsequent to said output of said two-modulus variable frequency divider circuit can respond with a maximum response time to said one change in condition of said output of said divide by 2 N frequency divider arrangement, whereby slower response components can be used in said subsequent frequency divider circuit; said final one of those divide by 2 frequency dividers of said divide by 2 N frequency divider arrangement which provide outputs to said monitor includes a non-inverted output terminal and an inverted output terminal, and said signal converting circuit selectively couples said non-inverted and inverted output terminals to said monitor in accordance with a control signal externally applied.

Claim 10

A two-modulus variable frequency-divider circuit comprising: a variable-frequency divider having an input for receiving a signal to be frequency divided and having a frequency dividing factor that can be selectively set to a particular one of at least two values in accordance with a frequency dividing factor setting signal; a divide by 2 N frequency-divider arrangement having an input for receiving a frequency divided output from said variable-frequency divider, said divide by 2 N frequency-divider arrangement comprising a number, N, of divide by 2 frequency dividers, where N is an integer; an output; a monitor for monitoring an output of at least one of said divide by 2 frequency dividers of said divide by 2 N frequency-divider arrangement, a monitor output from said monitor being fed back to said variable-frequency divider as said frequency dividing factor setting signal; a signal converting circuit connected between said monitor and the output of the final one of those divide by 2 frequency dividers of said divide by 2 N frequency-divider arrangement which provides output to said monitor; said signal converting circuit including means for selectively inverting or non-inverting said frequency divided output from said final one of said divide by 2 frequency dividers in said divide by 2 N frequency divider arrangement; and said means for selectively inverting or non-inverting being settable at either of its conditions to make effective a one of a positive-going and a negative-going change in condition of said output of said divide by 2 N frequency-divider arrangement so that a frequency divider circuit connected subsequent to said output of said two-modulus variable frequency divider circuit can respond with a maximum response time to said one change in condition of said output of said divide by 2 N frequency divider arrangement, whereby slower response components can be used in said subsequent frequency divider circuit; said final one of those divide by 2 frequency dividers of said divide by 2 N frequency divider arrangement which provide outputs to said monitor includes a non-inverted output terminal and an inverted output terminal, and said signal converting circuit selectively couples said non-inverted and inverted output terminals to said monitor in accordance with a control signal externally applied.

Claim 11

A frequency-divider circuit and a subsequent frequency divider circuit with respectively different response times for dividing a high-frequency signal to produce a reference signal related to said high-frequency signal by an integer division ratio, comprising: a two-modulus variable-frequency divider; means in said two-modulus variable-frequency divider for receiving a modulus control signal; said modulus control signal having first and second conditions; said two-modulus variable-frequency divider being responsive for producing an output signal for a first predetermined number of cycles of said high-frequency signal when said modulus control signal is in said first condition; said two-modulus variable-frequency divider being further responsive for producing an output signal for a second predetermined number of cycles of said high-frequency signal when said modulus control signal is in said second condition; a subsequent circuit having a slower response time than said two-modulus variable frequency divider circuit receiving said output signal and producing said reference signal in response to a first predetermined number of cycles of said output signal; said subsequent circuit being effective for producing a MOD signal after a second predetermined number of cycles of said output signal; said second predetermined number being less than said first predetermined number; a monitor; said monitor receiving said MOD signal; at least one divide-by-two counter in said two-modulus variable-frequency divider; an output of said at least one divide-by-two counter being connected to said monitor; an output of said monitor being said modulus control signal; and means for maximizing a period during which said subsequent circuit must respond to said output signal, whereby lower cost components may be used in said subsequent circuit.

Claim 12

A frequency-divider circuit and a subsequent frequency divider circuit with respectively different response times for dividing a high-frequency signal to produce a reference signal related to said high-frequency signal by an integer division ratio, comprising: a two-modulus variable-frequency divider; means in said two-modulus variable-frequency divider for receiving a modulus control signal; said modulus control signal having first and second conditions; said two-modulus variable-frequency divider being responsive for producing an output signal for a first predetermined number of cycles of said high-frequency signal when said modulus control signal is in said first condition; said two-modulus variable-frequency divider being further responsive for producing an output signal for a second predetermined number of cycles of said high-frequency signal when said modulus control signal is in said second condition; a subsequent circuit having a slower response time than said two-modulus variable frequency divider circuit receiving said output signal and producing said reference signal in response to a first predetermined number of cycles of said output signal; said subsequent circuit being effective for producing a MOD signal after a second predetermined number of cycles of said output signal; said second predetermined number being less than said first predetermined number; a monitor; said monitor receiving said MOD signal; at least one divide-by-two counter in said two-modulus variable-frequency divider; an output of said at least one divide-by-two counter being connected to said monitor; an output of said monitor being said modulus control signal; and means for maximizing a period during which said subsequent circuit must respond to said output signal, whereby lower cost components may be used in said subsequent circuit.

Claim 13

Apparatus according to claim 8, wherein said means for maximizing includes: means for selectively inverting said output signal; and said means for selectively inverting being set for one of inverting and non-inverting depending on a condition providing a maximum time for said subsequent circuit to produce said MOD signal.

Claim 14

Apparatus according to claim 8, wherein said means for maximizing includes: means for selectively inverting said output of said at least one divide-by-two counter; and said means for selectively inverting being set for one of inverting and non-inverting depending on a condition providing a maximum time for said subsequent circuit to produce said MOD signal.

Claim 15

Apparatus according to claim 9 or 10, wherein said means for selectively inverting includes means responsive to external control for selecting said inverting or non-inverting condition.