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US5084842A
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Dynamic random access memory with enhanced sense-amplifier circuit
Assignee: Toshiba Corp
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Filing: 1990-06-12
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Granted: 1992-01-28
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Expires: 2010-06-12
Abstract
Abstract A dynamic random access memory has a substrate, plural pairs of parallel bit lines provided on the substrate, parallel word lines insulatively crossing the parallel bit lines to define cross points therebetween, and memory cells provided at the cross points. Each memory cell has a data storage capacitor and a transistor. Sense amplifiers are provided at bit line pairs, respectively, to sense a data voltage. A discharge control section, which is associated with the sense amplifiers, forms discharge paths branched between the bit line pairs and the substrate grounded to progress the discharging of charges, when a certain word line is designated and a memory cell is selected from those memory cells which are connected to the certain word line, whereby the operational speed of the memory is increased.
Inventors
- 👤 Kenji Tsuchida
- 👤 Yukihito Oowaki
- 👤 Daisaburo Takashima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 19:43
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4091; G11C11/4094; G11C11/4096; H; H10; H10B; H10B12/00; H10B12/30
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
115 words
A semiconductor memory device comprising: a substrate; parallel bit lines provided on said substrate; parallel word lines insulatively crossing said bit lines above said substrate to define cross points therebetween; memory cells provided at the cross points, each of said memory cells having a data storage capacitor and a transistor; sense amplifier means connected to said bit lines, for sensing a data voltage; and discharge control means, associated with said sense amplifier means, for forming a discharge path branched between said bit lines and a ground potential when a certain word line is specified and a memory cell is selected from those memory cells connected to said certain work line, thereby progressing discharging of charges.
Claim 2
Dependent Claim
115 words
A semiconductor memory device comprising: a substrate; parallel bit lines provided on said substrate; parallel word lines insulatively crossing said bit lines above said substrate to define cross points therebetween; memory cells provided at the cross points, each of said memory cells having a data storage capacitor and a transistor; sense amplifier means connected to said bit lines, for sensing a data voltage; and discharge control means, associated with said sense amplifier means, for forming a discharge path branched between said bit lines and a ground potential when a certain word line is specified and a memory cell is selected from those memory cells connected to said certain work line, thereby progressing discharging of charges.
Claim 3
Dependent Claim
47 words
The device according to claim 1, wherein said discharge control means comprises: a common line commonly connected to said sense amplifier means; and switch means, connected to said common line, for, when selectively rendered conductive, permitting charges on said bit lines to be discharged to flow therein.
Claim 4
Dependent Claim
33 words
The device according to claim 2, wherein said discharge control means further comprises discharge line means, connected to said switch means and kept at a selected constant potential, for discharging a discharge current.
Claim 5
Dependent Claim
13 words
The device according to claim 3, wherein said switch means includes a transistor.
Claim 6
Dependent Claim
40 words
The device according to claim 4, wherein said discharge line means includes a discharge line parallel to said bit lines, said discharge line being connected between said transistor and either a ground potential of said device or a source potential.
Claim 7
Dependent Claim
15 words
The device according to claim 3, wherein said switch means includes transistors connected in parallel.
Claim 8
Dependent Claim
49 words
The device according to claim 6, wherein said discharge line means includes a preselected number of discharge lines parallel to said bit lines, each of said discharge lines being connected between an associated one of said transistors and either a ground potential of said device or a source potential.
Claim 9
Dependent Claim
45 words
The device according to claim 3, wherein said memory cells are divided into a plurality of memory groups arranged to define gap spaces therebetween on said substrate, and said switch means and said discharge line means are arranged in selected regions in said gap spaces.
Claim 10
Dependent Claim
47 words
The device according to claim 8, wherein said word lines have a double-layered structure having a conductive overlying layer and a conductive underlying layer electrically connected together by contact portions, and said selected regions are defined on said substrate as regions where said contact portions are provided.
Claim 11
Dependent Claim
157 words
A dynamic random access memory comprising: a substrate having a memory area and a peripheral area; plural pairs of parallel bit lines provided on said substrate; parallel word lines crossing said bit line pairs in said memory area above said substrate to define cross points therebetween; memory cells provided at said cross points and each having a capacitor and a transistor; first decoder means for selectively designating said word lines; second decoder means for selectively designating said bit line pairs; sense amplifier means, provided for each of said bit line pairs, for sensing a data voltage; and sense amplifier driver means, connected to said sense amplifier means, for driving said sense amplifier means, said sense amplifier means comprising, a main driver provided in said peripheral area of said substrate, and at least one subdriver provided in said memory area of said substrate, said subdriver providing an additional charge discharge path with respect to said bit line pairs.
Claim 12
Dependent Claim
157 words
A dynamic random access memory comprising: a substrate having a memory area and a peripheral area; plural pairs of parallel bit lines provided on said substrate; parallel word lines crossing said bit line pairs in said memory area above said substrate to define cross points therebetween; memory cells provided at said cross points and each having a capacitor and a transistor; first decoder means for selectively designating said word lines; second decoder means for selectively designating said bit line pairs; sense amplifier means, provided for each of said bit line pairs, for sensing a data voltage; and sense amplifier driver means, connected to said sense amplifier means, for driving said sense amplifier means, said sense amplifier means comprising, a main driver provided in said peripheral area of said substrate, and at least one subdriver provided in said memory area of said substrate, said subdriver providing an additional charge discharge path with respect to said bit line pairs.
Claim 13
Dependent Claim
62 words
The memory according to claim 10, wherein said subdriver comprises discharge control means, associated with said sense amplifier means, for forming a discharge path branched between said bit lines and said substrate to progress charging of charges when a certain word line is designated and a memory cell is selected from those memory cells which are connected to said certain word line.
Claim 14
Dependent Claim
85 words
The device according to claim 11, wherein said discharge control means comprises: a common line commonly connected to said sense amplifier means; switching transistors, connected in parallel to said common line, for, when selectively rendered conductive, permitting charges on said bit lines to be discharged to flow therein; and a plurality of parallel potential applying lines, provided between said switching transistors and either a ground potential of said memory or a source potential, for discharging a discharge current to thereby form a branched discharge path.
Claim 15
Dependent Claim
90 words
The device according to claim 12, wherein said memory area is divided into a plurality of rectangular memory blocks each of which is divided into subblocks having a first selected number of rows and a second selected number of columns, first gap regions where contact portions for said word lines are arranged are defined between said subblocks to run in parallel to said bit line pairs, and second gap regions where said sense amplifier means is arranged are defined between said subblocks to run in parallel to said word lines.
Claim 16
Dependent Claim
35 words
The device according to claim 13, wherein said switching transistors are arranged together with said sense amplifier means in said second gap regions and said potential applying lines are arranged in said first gap regions.
References Cited (Backward Citations)
US4803664A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-01-27 | 1995-07-29 | 1996-01-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-01-27 | 1999-07-29 | 2000-01-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-01-27 | 2003-07-29 | 2004-01-28 | $7700.00 | Window Closed / Lapsed |