Patent US5083189A successfully refreshed from Google Patents.
US5083189A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Resin-sealed type IC device
Assignee: Toshiba Corp
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Filing: 1990-04-09
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Granted: 1992-01-21
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Expires: 2010-04-09
Abstract
Abstract A resin-sealed type integrated circuit device is disclosed which comprises an island constituting a lead frame, and a plurality of hybrid units which, together with the island, are integrally sealed with a resin. The device has the advantages of simplicity of design and reduced size, but without any loss of quality.
Inventors
- 👤 Hiromichi Sawaya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 10:29
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/10; H10W74/131; H10W70/00; H10W70/40; H10W70/464; H10W70/468; H10W72/00; H10W72/50; H10W74/111; H10W74/124; H10W90/00; H10W90/811; H10W72/541; H10W72/547; H10W72/5473; H10W72/851; H10W72/874; H10W72/884; H10W90/701; H10W90/751; H10W90/756
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
147 words
A multi-hybrid integrated circuit device with a resin-sealed type package comprising: a lead frame having a plurality of separated island portions and a plurality of electrical lead portions positioned around said plurality of island portions; a plurality of hybrid units at least one of which is mounted on each of said plurality of island portions, each of said hybrid units having a circuit board, said circuit board including an insulating substrate and conductive interconnecting layers printed with a predetermined pattern formed thereon and a plurality of active or passive elements located over the circuit board and connected with corresponding interconnecting layers; a plurality of fine wires electrically connected to said hybrid units and said lead portion of said lead frame; and resin mold for sealing said plurality of island portions, inner portions of said lead portions, the hybrid units and the fine wires as an integral unit.
Claim 2
Dependent Claim
147 words
A multi-hybrid integrated circuit device with a resin-sealed type package comprising: a lead frame having a plurality of separated island portions and a plurality of electrical lead portions positioned around said plurality of island portions; a plurality of hybrid units at least one of which is mounted on each of said plurality of island portions, each of said hybrid units having a circuit board, said circuit board including an insulating substrate and conductive interconnecting layers printed with a predetermined pattern formed thereon and a plurality of active or passive elements located over the circuit board and connected with corresponding interconnecting layers; a plurality of fine wires electrically connected to said hybrid units and said lead portion of said lead frame; and resin mold for sealing said plurality of island portions, inner portions of said lead portions, the hybrid units and the fine wires as an integral unit.
Claim 3
Dependent Claim
32 words
The resin-sealed type integrated circuit device according to claim 1, in which said plurality of hybrid units are surrounded, in a non-contacting fashion, by a storage unit formed of an insulating material.
Claim 4
Dependent Claim
46 words
The resin-sealed type integrated circuit device according to claim 1, in which a conductor interconnection layer of said hybrid units is covered with an insulating film, the insulating film having a hole at a location corresponding to an electrode connection portion of said conductor interconnection layer.
Claim 5
Dependent Claim
23 words
The resin-sealed type integrated circuit device according to claim 1, in which said plurality of hybrid units each have an individual different function.
Claim 6
Dependent Claim
23 words
The resin-sealed type integrated circuit device according to claim 1, in which said plurality of hybrid units constitute a hybrid type integrated circuit.
Claim 7
Dependent Claim
67 words
The resin-sealed type integrated circuit device according to claim 1, in which said hybrid units each comprise an insulating substrate formed on said plurality of island portions, a conductor interconnection layer formed on the insulating substrate, a semiconductor chip, and wires one of which creates an electrical connection between said conductor interconnection layer and said semiconductor chip and between said conductor interconnection layer and a lead wire.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-01-20 | 1995-07-22 | 1996-01-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-01-20 | 1999-07-22 | 2000-01-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-01-20 | 2003-07-22 | 2004-01-21 | $7700.00 | Window Closed / Lapsed |