Motor driver interface fault detection circuit with dual mode fault detection

Claim 1

In an H-bridge electric motor drive apparatus comprising an electric power supply having supply and ground voltage terminals, a first pair of switching transistors connected in series with the power supply, a second pair of switching transistors connected in parallel with the first pair of switching transistors, and an electric motor having a first motor terminal connected to the junction of the first pair of switching transistors and a second terminal connected to the junction of the second pair of switching transistors, the apparatus comprising circuit apparatus responsive to an enable signal in a first condition to assume a not enabled state in which none of the switching transistors is activated and further responsive to the enable signal in a second condition to assume an enabled state in which one of the switching transistors in one of the first and second pairs is activated and the other transistor in the one of the first and second pairs of switching transistors may be activated, fault detection apparatus comprising, in combination: a first resistor connected from the first motor terminal to a first reference voltage and having a resistance much greater than the series impedance of the electric motor so as to be incapable of conducting motor operating current; a second resistor connected from the second motor terminal to a second reference voltage and having a resistance much greater than the series impedance of the electric motor so as to be incapable of conducting motor operating current; not enabled reference voltage generating apparatus comprising a voltage divider connected between the first and second reference voltages to generate a third reference voltage greater than the voltage at the first motor terminal with the switching transistors in an off condition and a fourth reference voltage lower than the voltage at the second motor terminal with the switching transistors in an off condition, the third and fourth reference voltages defining a not enabled voltage window therebetween; enabled reference voltage generating apparatus effective to generate a fifth reference voltage above the ground voltage terminal at least by the conducting voltage of one of the switching transistors and a sixth reference voltage below the supply voltage terminal by the conducting voltage of the one of the switching transistors, the fifth reference voltage and supply voltage defining a first enabled voltage window therebetween and the sixth reference voltage and ground defining a second enabled voltage window therebetween; fault detection apparatus responsive to the enable signal in its first condition to compare the voltages at the first and second motor terminals with each of the third and fourth reference voltages and signal a fault if the voltage at one of the first and second motor terminals is outside the not enabled voltage window and further responsive to the enable signal in its second condition to compare the voltage at one of the first and second motor terminals with one of the fifth and sixth reference voltages and signal a fault if the voltage at the one of the first and second motor terminals is outside the corresponding one of the first and second enabled voltage windows.