Method for forming a connection device in a semiconductor device

Claim 1

In a semiconductor device comprising a first insulating layer formed on a silicon substrate, an internal connection line formed on a portion of the first insulating layer and a second insulating layer formed on the entire surface, a method for forming a connection device for semiconductor device comprising forming a contact hole by etching a portion of the second insulating layer to expose a portion of the top surface of the internal connection line, the method further comprising the steps of: forming a first insulating layer on a silicon substrate; forming a first conductive material layer for internal connection line on the first conductive material layer; arranging an internal connection line mask on the first conductive material layer with the same width as that of a contact mask which is utilized to form a contact hole in order to reduce the width of an internal connection line, and forming the internal connection line by a mask patterning process of the conductive material layer; forming a second insulating layer on the entire surface; forming a contact hole having side walls by etching a portion of the second insulating layer on the internal connection line with a contact mask pattering process, thereby exposing the top surface of the internal connection line; forming an insulating film on the entire surface, and forming insulating film spacers on the side walls of the contact hole by anisotropically etching the insulating film; and depositing a second conductive material layer on the entire surface including the exposed surface of internal connection line, thereby electrically the second conductive material layer to the reduced internal connection line.

Claim 4

A method for electrically connecting a bit line to a source electrode of MOSFETs in a semiconductor device, the method comprising: sequentially depositing a gate oxide film and a conductive material layer for gate electrodes on a silicon substrate; arranging a gate electrode mask to form gate electrodes which are spaced apart and formed on respective gate oxide layers such that a contact mask which when positioned within the space between the gate electrodes provides gap, for mask misalignment and critical dimension loss during the contact mask patterning process, of less than about 0.3 micrometer, separating each gate electrode from the respective proximate side of the contact mask; forming the gate oxide films and gate electrodes by the mask patterning process of the gate oxide film and the conductive material layer utilizing the gate electrode mask; forming a source electrode in the silicon substrate positioned between the gate electrodes; forming a drain electrode in the silicon substrate operatively positioned proximate each gate electrode to provide MOSFETs; depositing an insulating layer on the entire surface and planarizing the insulating layer; forming an etch stop layer on the entire surface; forming a contact hole having a side wall to expose the source electrode by utilizing the contact mask and etching a portion of the etch stop layer and a portion of the insulating layer above the source electrode by the contact mask patterning process; depositing a second insulating layer over the entire surface; removing the etch stop layer and the second insulating layer from the surface except for a portion of the second insulating layer deposited on the sidewall of the contact hole thereby providing an insulating film spacer on the sidewall of the contact hole to ensure electrical isolation of the gate electrode proximate the sidewall of the contact hole; and depositing a conductive layer for a bit line on the entire surface to electrically connect the source electrode to the bit line.

Claim 5

A method for electrically connecting a bit line to a source electrode of MOSFETs in a semiconductor device, the method comprising: sequentially depositing a gate oxide film and a conductive material layer for gate electrodes on a silicon substrate; arranging a gate electrode mask to form gate electrodes which are spaced apart and formed on respective gate oxide layers such that a contact mask which when positioned within the space between the gate electrodes provides gap, for mask misalignment and critical dimension loss during the contact mask patterning process, of less than about 0.3 micrometer, separating each gate electrode from the respective proximate side of the contact mask; forming the gate oxide films and gate electrodes by the mask patterning process of the gate oxide film and the conductive material layer utilizing the gate electrode mask; forming a source electrode in the silicon substrate positioned between the gate electrodes; forming a drain electrode in the silicon substrate operatively positioned proximate each gate electrode to provide MOSFETs; depositing an insulating layer on the entire surface and planarizing the insulating layer; forming an etch stop layer on the entire surface; forming a contact hole having a side wall to expose the source electrode by utilizing the contact mask and etching a portion of the etch stop layer and a portion of the insulating layer above the source electrode by the contact mask patterning process; depositing a second insulating layer over the entire surface; removing the etch stop layer and the second insulating layer from the surface except for a portion of the second insulating layer deposited on the sidewall of the contact hole thereby providing an insulating film spacer on the sidewall of the contact hole to ensure electrical isolation of the gate electrode proximate the sidewall of the contact hole; and depositing a conductive layer for a bit line on the entire surface to electrically connect the source electrode to the bit line.