US5080988A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Biasing scheme for improving latitudes in the tri-level xerographic process
Assignee: Xerox Corp
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Filing: 1989-11-22
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Granted: 1992-01-14
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Expires: 2009-11-22
Abstract
Abstract The operating latitude of the tri-level xerographic process is improved by replacing the standard DC bias that is applied to one or both of the developer housings in conventional tri-level imaging with a chopped DC (CDC) developer bias. Chopped DC biasing is the alternate application of two discrete bias voltages to a developer stucture in a periodic fashion at a given frequency, with the period of each cycle divided up between the two bias levels at a duty cycle of from 5%-10% or 90%-95% depending upon which of the two developer structures is being biased. In the case of the DAD developer structure the duty cycle of higher of the two biases is 5%-10% and in case of a CAD developer structure the duty cycle of higher of the two biases is 90%-95%.
Inventors
- 👤 Richard P. Germain
- 👤 James E. Williams
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 06:46
CPC Classifications
G; G03; G03G; G03G13/00; G03G13/01; G03G13/013; G03G15/00; G03G15/01; G03G15/0105; G03G15/0121
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
95 words
In the method of developing tri-level latent electrostatic images contained on a charge retentive imaging surface wherein the tri-level images include two image areas at different voltage levels and a background area, the steps of: providing separate developer structures for developing said two image areas; and alternately applying two voltage biases to one of said developer structures for different periods of time for developing one of said image areas; and alternately applying two voltage biases to the other of said developer structures for different periods of time for developing the second of said image areas.
Claim 2
Dependent Claim
95 words
In the method of developing tri-level latent electrostatic images contained on a charge retentive imaging surface wherein the tri-level images include two image areas at different voltage levels and a background area, the steps of: providing separate developer structures for developing said two image areas; and alternately applying two voltage biases to one of said developer structures for different periods of time for developing one of said image areas; and alternately applying two voltage biases to the other of said developer structures for different periods of time for developing the second of said image areas.
Claim 3
Dependent Claim
24 words
The method according to claim 1 wherein the voltage level of said background area is intermediate the voltage levels of said two image areas.
Claim 4
Dependent Claim
25 words
The method according to claim 2 wherein said step of applying one of said voltage biases is effected at a duty cycle of approximately 6%.
Claim 5
Dependent Claim
20 words
The method according to claim 3 wherein the frequency of the application of said voltage biases is approximately 5 kHz.
Claim 6
Dependent Claim
16 words
The method according to claim 4 wherein one of said image areas is a DAD image.
Claim 7
Dependent Claim
17 words
The method according to claim 5 wherein the other of said image areas is a CAD image.
Claim 8
Dependent Claim
32 words
The method according to claim 1 wherein said step of applying one of said voltage biases to the other of said developer structures is effected at a duty cycle of approximately 6%.
Claim 9
Dependent Claim
26 words
The method according to claim 7 wherein the frequency of the application of said voltage biases applied to said other developer structure is approximately 5 kHz.
Claim 10
Dependent Claim
18 words
The method according to claim 8 wherein said image areas and said background area at the same polarity.
References Cited (Backward Citations)
US4078929A
Cited
JPS54138439A
Cited
US4632054A
Cited
US4761668A
Cited
US4771314A
Cited
US4761672A
Cited
US4811046A
Cited
US4833504A
Cited
US4868611A
Cited
US4847655A
Cited
US4998139A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-01-13 | 1995-07-15 | 1996-01-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-01-13 | 1999-07-15 | 2000-01-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-01-13 | 2003-07-15 | 2004-01-14 | $7700.00 | Window Closed / Lapsed |