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US5079520A
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Interpolating phase-locked loop frequency synthesizer
Assignee: Qualcomm Inc
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Filing: 1991-01-07
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Granted: 1992-01-07
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Expires: 2011-01-07
Abstract
Abstract The invention concerns are interpolating frequency synthesizer based on digital phase locking, with which frequencies can be produced which lie between frequencies defined by integer divisors. Traditional frequency synthesizers employ frequency dividers in which the dividing ratio is an integer. The circuit of the invention comprises member (8, 9), in one of which the reference frequency (f o ) or the VCO frequency (f x ), or the frequency obtained from them by division, is multiplied with a coefficient L and in the other member the corresponding frequency is multiplied by L+ ΔL; and members (2, 7), in which the first pulses going to the phase detector (3) are lengthened by a time corresponding to a given integer number k1 of pulses formed in the number (8), and the other pulses are lengthened by a time corresponding to a given integer number k2 of pulses formed in the member (9).
Inventors
- 👤 Juha Rapeli
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 06:48
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/197; H03L7/1974
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
246 words
A frequency synthesizer based on a digital phase-locked loop (PLL) wherein as frequencies of the input signals to a phase detector (3) serves a frequency divided from a reference pulse frequency (f o ) in a divider (1) with a number M and a frequency obtained from the pulse frequency (f x ) produced by a voltage-controlled oscillator VCO (5) by division in dividers (6), the output signal of the phase detector (3) filtered in a loop filter (4) controls the voltage-controlled oscillator VCO, characterized in that it comprises: members (8,9), in one of which the reference signal frequency (f o ) or the frequency obtained therefrom by division in the divider (1), or the output frequency (f x ) of the oscillator VCO (5) or the frequency obtained therefrom by division in a divider (6), is multiplied with a coefficient L and in the other the corresponding frequency is multiplied with a coefficient L+ΔL, and members (2,7), in one (2) of said members the pulses of a first input signal, going to the phase detector (3), are each separately lengthened by a time corresponding to a given integer number k1 of pulse lengths of the pulses formed in the member (9), and in the other member (7) the pulses of a second input signal, going to the phase detector (3), are each separately lengthened by a time corresponding to a given integer number k2 of pulse lengths of the pulses formed in the member (8).
Claim 2
Dependent Claim
246 words
A frequency synthesizer based on a digital phase-locked loop (PLL) wherein as frequencies of the input signals to a phase detector (3) serves a frequency divided from a reference pulse frequency (f o ) in a divider (1) with a number M and a frequency obtained from the pulse frequency (f x ) produced by a voltage-controlled oscillator VCO (5) by division in dividers (6), the output signal of the phase detector (3) filtered in a loop filter (4) controls the voltage-controlled oscillator VCO, characterized in that it comprises: members (8,9), in one of which the reference signal frequency (f o ) or the frequency obtained therefrom by division in the divider (1), or the output frequency (f x ) of the oscillator VCO (5) or the frequency obtained therefrom by division in a divider (6), is multiplied with a coefficient L and in the other the corresponding frequency is multiplied with a coefficient L+ΔL, and members (2,7), in one (2) of said members the pulses of a first input signal, going to the phase detector (3), are each separately lengthened by a time corresponding to a given integer number k1 of pulse lengths of the pulses formed in the member (9), and in the other member (7) the pulses of a second input signal, going to the phase detector (3), are each separately lengthened by a time corresponding to a given integer number k2 of pulse lengths of the pulses formed in the member (8).
Claim 3
Dependent Claim
100 words
PLL frequency synthesizer according to claim 1, characterized in that the members (8,9) comprise a delay chain of length L or L+ΔL composed of consecutive delay register elements and the speed of which is locked so that the delay of one delay element (41) corresponds to the 1/L or 1/(L+ΔL) fraction of the period length of the pulse frequency coming to the member (8,9), the lengthening of the pulses going to the phase detector (3) in the manner indicated by integers k1 and k2 taking place with the aid of the edge of the pulse progressing in the delay chain.
Claim 4
Dependent Claim
91 words
PLL frequency synthesizer according to claim 2, characterized in that the progress through the delay chain of length L and L+ΔL of the edge of the pulse coming to the members (8,9) is synchronized to take place during the period of said incoming pulse and the lengthening in desired amount of the pulses coming to the phase detector takes place by directing to the phase detector (3) the output of that delay element of the respective delay chain of which the sequential number is indicated by the integer k1 and k2.
Claim 5
Dependent Claim
98 words
PLL frequency synthesizer according to claim 3, characterized in that each pulse coming to the phase detector (3) is lengthened in the members (2,9; 7,8) relative to the preceding pulse by updating the coefficients k1 and k2 for every pulse in that to the delay of the next pulse is added its delay by shifting in the delay chain the output k1 or the output k2 by the amount of the delay gate cyclically forward, and in case no delay is being used in the delay chains, on transgression of this point one whole clock pulse is added.
Claim 6
Dependent Claim
25 words
PLL frequency synthesizer according to any one of the preceding claims, characterized in that in the coefficient L+ΔL , ΔL has the value+1 or -1.
Claim 7
Dependent Claim
28 words
PLL frequency synthesizer according to claim 1, characterized in that the multiplication of frequencies in the members (8,9) takes place with the aid of controlled, phase-locked inverter chains.
References Cited (Backward Citations)
US4611230A
Cited
US4868524A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-01-06 | 1995-07-08 | 1996-01-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-01-06 | 1999-07-08 | 2000-01-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-01-06 | 2003-07-08 | 2004-01-07 | $7700.00 | Window Closed / Lapsed |