Memory input data test arrangement

Claim 1

A memory means having a control circuit for selecting between a retrieval procedure for retrieving from therein information to be presented at data outputs thereof, a direct storage procedure for storing therein information that is presented at data inputs thereof, and a storage with test procedure for storing therein information presented at said data inputs thereof and for passing such information presented at these said data inputs to said data outputs thereof, said selecting of said procedures and initiation of that one selected being under control of both a periodic system clock signal provided at a memory clock signal input terminal means of said memory means adapted for connection to a source of such a system clock signal and a system read/write signal provided at a memory read/write signal input terminal means of said memory means adapted for connection to a source of such a system read/write signal, said memory means comprising: a memory control and storage cell array means having a plurality storage cells therein each having at least one input thereof and one output thereof electrically connected in common, said storage cells each being capable of storing information therein presented at its input and alternatively being capable of providing information previously stored therein at its output, said storage cell inputs therein electrically connected to said memory means data inputs to receive information therein, said memory control and storage cell array means further having a control input for receiving a memory read/write signal to select whether said memory control and storage cell array means, in a period of said system clock signal, is to either store therein information provided at its said storage cell inputs or retrieve information previously stored therein to be presented at its said storage cell outputs; a set of memory output data latches having a data input electrically connected to said memory control and storage cell array means storage cell outputs, said set of memory output data latches having a data output electrically connected to said memory means data outputs, said set of memory output data latches each being capable of storing therein information occurring on a said memory output data latch data input so that such information is presented and maintained on its output even though there are subsequent changes in said information occurring at its input, or of preventing such storing of information therein but rather passing information changes provided at its input to its output as they occur, said set of memory output data latches further having a control input for receiving an output latch signal to select whether to permit storing of information provided at its inputs or passing changes therein to its outputs as they occur, and; a control circuit means comprising: a read/write indicator means having a pair of inputs one of which is electrically connected to said memory clock signal input terminal means and that one remaining being electrically connected to said memory read/write signal input terminal means, said read/write indicator means also having an output electrically connected to said memory control and storage cell array means control input, said read/write indicator means being capable of forming said memory read/write signal by providing an indication on said output thereof in each period of said system clock signal, based on an initial indication in said system read/write signal in that period, whether said memory control and storage cell array means is in that period to store information occurring on said memory means data inputs or to retrieve information stored therein for presentation on said memory means data outputs; and a latch control means having a pair of inputs one of which is electrically connected to said memory clock signal input terminal means and that one remaining being electrically connected to said memory read/write signal input terminal means, said latch control means also having an output electrically connected to said control input of said set of memory output data latches, said latch control means being (i) capable, in each period of said system clock signal in which said system read/write signal initial indication in that period indicates that said memory control and storage cell array means is to retrieve information, as aforesaid, of providing an indication during that period on said output thereof that said memory output data latch is to store information therein, as aforesaid, and (ii) capable, in each period of said system clock signal in which said system read/write signal initial indication in that period indicates that said memory control and storage cell array means is to store information, as aforesaid, of providing an indication during that period on said output thereof that said memory output data latch is to (a) store information therein as aforesaid for a first further indication in said system read/write signal in that period, and is to alternatively (b) prevent storage of information therein for an alternative second further indication in said system read/write signal in that period.

Claim 9

A method for operating a memory means in a storage-with-test mode to permit verifying, to an extent, of information presented at inputs thereof for storage therein and having a memory control and storage cell array means which can be directed by one logic state of a memory read/write control signal to store information presented at inputs thereof in a period of a periodic system clock signal, and can be directed by an opposite state of such a memory read/write control signal to retrieve information previously stored therein in a period of said system clock signal to be presented to outputs thereof, said memory control and storage cell array means having common interconnections on which information at inputs thereof can be presented to said memory control and storage cell array means for storage therein, and can also be presented directly from said inputs to an output latch means for verification, and on which information stored on said memory control and storage cell array means can be retrieved from storage therein and presented to said output latch means, said method comprising: providing to said memory means in a selected period of said system clock signal a system read/write signal having an initial logic state sufficient to cause said memory means to store therein information provided at its said inputs through forming said memory read/write control signal first logic state which state is maintained during said period of said system clock signal even though said system read/write control signal changes its logic state; providing information in said selected period to said memory control and storage cell array means at inputs thereof; changing in said selected period said initial logic state in said system read/write control signal and providing an output latch signal to said output latch means based on said change in said system read/write control signal logic state to cause said output latch means to pass information received on said common interconnections directly from said inputs to outputs of said memory means, including any changes in said information as they occur; and comparing said information passed through said output latch means with said information provided to said inputs of said memory means to determine whether any differences exist.

Claim 10

A method for operating a memory means in a storage-with-test mode to permit verifying, to an extent, of information presented at inputs thereof for storage therein and having a memory control and storage cell array means which can be directed by one logic state of a memory read/write control signal to store information presented at inputs thereof in a period of a periodic system clock signal, and can be directed by an opposite state of such a memory read/write control signal to retrieve information previously stored therein in a period of said system clock signal to be presented to outputs thereof, said memory control and storage cell array means having common interconnections on which information at inputs thereof can be presented to said memory control and storage cell array means for storage therein, and can also be presented directly from said inputs to an output latch means for verification, and on which information stored on said memory control and storage cell array means can be retrieved from storage therein and presented to said output latch means, said method comprising: providing to said memory means in a selected period of said system clock signal a system read/write signal having an initial logic state sufficient to cause said memory means to store therein information provided at its said inputs through forming said memory read/write control signal first logic state which state is maintained during said period of said system clock signal even though said system read/write control signal changes its logic state; providing information in said selected period to said memory control and storage cell array means at inputs thereof; changing in said selected period said initial logic state in said system read/write control signal and providing an output latch signal to said output latch means based on said change in said system read/write control signal logic state to cause said output latch means to pass information received on said common interconnections directly from said inputs to outputs of said memory means, including any changes in said information as they occur; and comparing said information passed through said output latch means with said information provided to said inputs of said memory means to determine whether any differences exist.