Patent US5073508A successfully refreshed from Google Patents.
US5073508A
Expired / Lapsed
US
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Method of manufacturing an integrated semiconductor circuit including a bipolar heterojunction transistor and/or buried resistors
Assignee: US Philips Corp
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Filing: 1990-09-14
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Granted: 1991-12-17
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Expires: 2010-09-14
Abstract
Abstract The invention relates to a method of manufacturing a non-planar HBT transistor comprising first the step of forming the emitter, the step of etching the device around the emitter as far as the level of the base layer, exposing a region for the collector contact, the emitter being protected, and then the step of forming the base contact by self-alignment on the emitter and the collector. This method utilizes steps of profile inversion, during which two dielectric layers of different materials are successively deposited, the first of which has a uniform thickness and the second of which has a non-uniform thickness and which are etched at different rates in order to cause chosen patterns to appear. The invention moreover permits forming concomitantly buried resistors. The device obtained is particularly compact and performant and the method requires only a very limited number of masking steps, which can be realized with a non-critical resolution.
Inventors
- 👤 Claudine Villalon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:38
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/021; H10D62/00; H10D62/80; H10D62/82; H10D62/824; H10D62/85; H10D62/854; H10D64/00; H10D64/01; H10D64/011; H10D84/00; H10D84/01; H10D84/02; H10D84/05; Y; Y10; Y10S; Y10S148/00; Y10S148/011; Y10S148/072
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
457 words
A method of manufacturing a semiconductor integrated circuit including at least one heterojunction bipolar transistor (HBT), said method comprising the steps of (a) forming on a substrate of semiconductor material in sequence at least one first semiconductor layer of a first conductivity type, at least one second semiconductor layer of a second conductivity type, and at least one third semiconductor layer of said first conductivity type, wherein p-n junctions are formed between said first and second semiconductor layers and between said second and third semiconductor layers, and wherein at least one of said p-n junctions is a heterojunction; (b) forming a first mask on said third semiconductor layer, said first mask having at least two openings; (c) etching said third semiconductor layer as far as said second semiconductor layer through said first mask to produce a relief structure having a height y 1 , said relief having said third semiconductor layer for an emitter; (d) forming a first uniform dielectric layer having a first opening at a surface of said relief; (e) forming a second mask over said first uniform dielectric layer including said first opening and forming at least one second opening in said second mask, said second opening being laterally separated from said relief; (f) etching as far as said first semiconductor layer through said second opening to form at least one cavity, said cavity having a transverse dimension x 1 , where y 1 <x 1 /2, said first semiconductor layer becoming a collector; (g) removing remaining portions of said second mask, and removing any remaining portions of said first mask from said relief; (h) forming first metallic contact layers for said emitter in said first opening and said collector in said second opening; (j) forming a uniform second dielectric layer to a thickness y 2 , where y 1 <y 2 <x 1 /2, said second dielectric layer being a material etched at a same rate as said first dielectric layer; (k) forming a planarizing layer on said second dielectric layer, and planarizing as far as said first dielectric layer; (l) etching remaining portions of said planarizing layer, said second dielectric layer and said first dielectric layer as far as said second semiconductor layer, said planarizing layer being etched at a rate higher than an etching rate of said first and second dielectric layers, wherein side edges of said emitter remain covered by said first dielectric layer, and wherein remaining edges of said cavity remain covered by said second dielectric layer; (m) forming a third mask having a third opening self-aligned about said emitter; said third opening exposing said second semiconductor layer, said second semiconductor layer becoming a base; and (n) forming second metallic contact layers for said base in said third opening.
Claim 2
Independent Claim
457 words
A method of manufacturing a semiconductor integrated circuit including at least one heterojunction bipolar transistor (HBT), said method comprising the steps of (a) forming on a substrate of semiconductor material in sequence at least one first semiconductor layer of a first conductivity type, at least one second semiconductor layer of a second conductivity type, and at least one third semiconductor layer of said first conductivity type, wherein p-n junctions are formed between said first and second semiconductor layers and between said second and third semiconductor layers, and wherein at least one of said p-n junctions is a heterojunction; (b) forming a first mask on said third semiconductor layer, said first mask having at least two openings; (c) etching said third semiconductor layer as far as said second semiconductor layer through said first mask to produce a relief structure having a height y 1 , said relief having said third semiconductor layer for an emitter; (d) forming a first uniform dielectric layer having a first opening at a surface of said relief; (e) forming a second mask over said first uniform dielectric layer including said first opening and forming at least one second opening in said second mask, said second opening being laterally separated from said relief; (f) etching as far as said first semiconductor layer through said second opening to form at least one cavity, said cavity having a transverse dimension x 1 , where y 1 <x 1 /2, said first semiconductor layer becoming a collector; (g) removing remaining portions of said second mask, and removing any remaining portions of said first mask from said relief; (h) forming first metallic contact layers for said emitter in said first opening and said collector in said second opening; (j) forming a uniform second dielectric layer to a thickness y 2 , where y 1 <y 2 <x 1 /2, said second dielectric layer being a material etched at a same rate as said first dielectric layer; (k) forming a planarizing layer on said second dielectric layer, and planarizing as far as said first dielectric layer; (l) etching remaining portions of said planarizing layer, said second dielectric layer and said first dielectric layer as far as said second semiconductor layer, said planarizing layer being etched at a rate higher than an etching rate of said first and second dielectric layers, wherein side edges of said emitter remain covered by said first dielectric layer, and wherein remaining edges of said cavity remain covered by said second dielectric layer; (m) forming a third mask having a third opening self-aligned about said emitter; said third opening exposing said second semiconductor layer, said second semiconductor layer becoming a base; and (n) forming second metallic contact layers for said base in said third opening.
Claim 3
Dependent Claim
103 words
A method according to claim 1, wherein said step (d) is carried out by the sub-steps of: (i) depositing said first dielectric layer to a uniform thickness e 1 on both said second semiconductor layer and on said relief, (ii) depositing a planarization layer on said first dielectric layer, (iii) uniformly dry etching said planarization layer until said first dielectric layer appears above said relief, (iv) anisotropically dry etching both said first dielectric layer and remaining portions of said planarization layer, said first dielectric layer being etched at a rate exceeding that of said planarization layer until said surface of said relief appears.
Claim 4
Dependent Claim
45 words
A method according to claim 2, wherein said first and second dielectric layers are selected from silica (SiO 2 ) and silicon nitride (Si 3 N 4 ), and wherein said planarizing layer and said planarization layer are selected from photosensitive lacquers and polymerizable resins.
Claim 5
Dependent Claim
66 words
A method according to claim 2, wherein said step (h) is carried out by the sub-steps of: (i) uniformly etching said planarizing layer and said second dielectric layer, and (ii) ion machining said metallic contact layers, and wherein said metallic contact layer for said emitter remains because a portion of said second dielectric layer remains at a surface of said metallic contact layer for said emitter.
Claim 6
Dependent Claim
139 words
A method according to claim 4, wherein buried resistors of low ohmic values are simultaneously formed with said HBT by the additional steps of (i) during said step (e) forming additional openings in said second mask, said additional openings being laterally separated from both said relief and said second opening; (ii) during said step (f) etching at least two second cavities to said first semiconductor layer through said additional openings, said first semiconductor layer being a resistive semiconductor layer; (iii) depositing a further mask in one of said two second cavities, said further mask protecting an effective region of a resistor at a surface of said resistive semiconductor layer; and (iv) during said step (h) forming another of said first metallic contact layers in another of said two second cavities to be in contact with said resistive semiconductor layer.
Claim 7
Dependent Claim
84 words
A method according to claim 5, wherein following said step (iv) but before said step (j), said further mask is removed; wherein said steps (j) and (l) also form said second dielectric layer and said planarizing layer in said at least two second cavities; wherein said step (l) also etches said planarizing layer and said second dielectric layer to expose said another of said first metallic contact layers; and wherein metallic contact lines are formed to said another of said first metallic contact layers.
Claim 8
Dependent Claim
30 words
A method according to claim 5, wherein said one of said two second cavities is formed with a transverse dimension of x 2 , where x 2 <x 1 .
Claim 9
Dependent Claim
55 words
A method according to claim 1, wherein a heterojunction bipolar transistor (HBT) is formed of a n-p-n type, said heterojunction being situated between said second and third semiconductor layers, and wherein said first and second metallic contact layers are of an ohmic type with respective semiconductor layers on which said metallic contact layers are formed.
Claim 10
Dependent Claim
51 words
A method according to claim 1, wherein between step (b) and step (c) a further step is carried out of forming isolation regions at surrounding sides of said first, second and third semiconductor layers to limit active regions, said isolation regions being formed by one of proton implantation and boron implantation.
Claim 11
Dependent Claim
227 words
A method according to claim 1, wherein said substrate of semiconductor material is formed of one of semi-insulating gallium arsenide and silicon provided with a layer of semi-insulating gallium arsenide, and wherein said step (a) is carried out by (i) forming said at least one first semiconductor layer from an about 0.5 μm thick layer of gallium arsenide having an n+ doping of about 5×10 18 at /cm 3 , and an about 0.5 μm thick layer of gallium arsenide having an n- doping of about 5×10 16 at /cm 3 ; (ii) forming said at least one second semiconductor layer from an about 0.1 μm thick layer of gallium arsenide having a p+ doping of about 10 19 at /cm 3 , and an about 0.01 μm thick layer of gallium arsenide being undoped; and (iii) forming said at least one third semiconductor layer from an about 0.03 μm thick layer of gallium aluminum arsenide having an n doping of about 5×10 17 at /cm 3 with an aluminum concentration progressively increasing from 0 to 25%, an about 0.2 μm thick layer of gallium aluminum arsenide having an n doping of about 5×10 17 at /cm 3 with an aluminum concentration of about 25%, and an about 0.2 μm thick layer of gallium arsenide having an n+ doping of about 5×10 18 at /cm 3 .
Claim 12
Dependent Claim
41 words
A method according to claim 1, wherein said first and second dielectric layers are selected from silica (SiO 2 ) and silicon nitride (Si 3 N 4 ), and wherein said planarizing layer is selected from photosensitive lacquers and polymerizable resins.
Claim 13
Dependent Claim
66 words
A method according to claim 1, wherein said step (h) is carried out by the sub-steps of: (i) uniformly etching said planarizing layer and said second dielectric layer, and (ii) ion machining said metallic contact layers, and wherein said metallic contact layer for said emitter remains because a portion of said second dielectric layer remains at a surface of said metallic contact layer for said emitter.
Claim 14
Dependent Claim
139 words
A method according to claim 1, wherein buried resistors of low ohmic values are simultaneously formed with said HBT by the additional steps of (i) during said step (e) forming additional openings in said second mask, said additional openings being laterally separated from both said relief and said second opening; (ii) during said step (f) etching at least two second cavities to said first semiconductor layer through said additional openings, said first semiconductor layer being a resistive semiconductor layer; (iii) depositing a further mask in one of said two second cavities, said further mask protecting an effective region of a resistor at a surface of said resistive semiconductor layer; and (iv) during said step (h) forming another of said first metallic contact layers in another of said two second cavities to be in contact with said resistive semiconductor layer.
Claim 15
Dependent Claim
84 words
A method according to claim 13, wherein following said step (iv) but before said step (j), said further mask is removed; wherein said steps (j) and (l) also form said second dielectric layer and said planarizing layer in said at least two second cavities; wherein said step (l) also etches said planarizing layer and said second dielectric layer to expose said another of said first metallic contact layers; and wherein metallic contact lines are formed to said another of said first metallic contact layers.
Claim 16
Dependent Claim
30 words
A method according to claim 13, wherein said one of said two second cavities is formed with a transverse dimension of x 2 , where x 2 <x 1 .
References Cited (Backward Citations)
US4617724A
Cited
US4889831A
Cited
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