Elevated CMOS

Claim 2

An integrated circuit device comprising: a dielectric layer having a recess therein; an n-type insulated gate vertical-channel field effect transistor having a conduction path within, and on one side of said recess; a p-type insulated gate vertical-channel field effect transistor having a conduction path within, and on another side of said recess opposite from said n-type insulated gate vertical-channel field effect transistor; and a control gate disposed in said recess between said n-type and p-type insulated gate vertical-channel field effect transistors connected to control current flow in the conduction path of both said n-type and said p-type insulated gate vertical-channel field effect transistors.

Claim 3

The device of claim 1, wherein said recess has substantially vertical sidewalls.

Claim 4

The device of claim 1, wherein said dielectric comprises an oxide of silicon.

Claim 5

The device of claim 1, wherein said control gate is part of a thin film layer which substantially fills said recess.

Claim 6

The device of claim 1, further comprising a plurality of other recesses in said dielectric layer containing respective n-channel transistors, wherein some of said respective n-channel transistors have width-to-length ratios (W/L) significantly different from the width-to-length ratios of others of said respective n-channel transistors.

Claim 7

An integrated circuit device comprising: a dielectric including therein a recess with substantially vertical sidewalls; a first insulated gate field effect transistor disposed within and adjacent to a first sidewall of said recess, said first insulated gate field effect transistor having a first source/drain and a second source/drain separated from one another vertically along said first sidewall of said recess by a channel region, and a second insulated gate field effect transistor disposed within and adjacent to a second sidewall of said recess, said second insulated gate field effect transistor having a first source/drain and a second source/drain separated from one another vertically along said second sidewall of said recess by a channel region; and a control gate disposed within said recess between the channel regions of said first and second insulated gate field effect transistors to control current flow in both said first and second insulated gate field effect transistors.

Claim 8

An integrated circuit device comprising: a dielectric including therein a recess with substantially vertical sidewalls; a first insulated gate field effect transistor disposed within and adjacent to a first sidewall of said recess, said first insulated gate field effect transistor having a first source/drain and a second source/drain separated from one another vertically along said first sidewall of said recess by a channel region, and a second insulated gate field effect transistor disposed within and adjacent to a second sidewall of said recess, said second insulated gate field effect transistor having a first source/drain and a second source/drain separated from one another vertically along said second sidewall of said recess by a channel region; and a control gate disposed within said recess between the channel regions of said first and second insulated gate field effect transistors to control current flow in both said first and second insulated gate field effect transistors.

Claim 9

The device of claim 6, wherein said control gate is part of a thin film layer which substantially fills said recess.

Claim 10

The device of claim 6, wherein each of said first and second insulated gate field effect transistor's channel region is essentially monocrystalline.

Claim 11

The device of claim 6, wherein each of said gate dielectrics is less than 300 Angstroms thick and consists essentially of silicon dioxide.

Claim 12

The device of claim 6, wherein said control gate contains more than 30% silicon by atomic weight and is not monocrystalline.

Claim 13

The device of claim 6, wherein said dielectric layer has a thickness in the range of 6000 A-15000 A inclusive.

Claim 14

The device of claim 6, wherein said first and second insulated gate field effect transistors each have a minimum thickness, between said control gate and one of said first and second sidewalls of said dielectric layer, in the range of 1000 A-8000 A inclusive.

Claim 15

The device of claim 6, further comprising a plurality of other recesses in said dielectric layer, at least one of which contains only a single transistor.

Claim 16

The device of claim 6, wherein said second source/drains of both said first and second insulated gate field effect transistors are ohmically contacted at a contact hole within said recess.

Claim 17

An integrated circuit device comprising: a substrate including a monocrystalline semiconductor portion including junction-isolated diffusions therein; a dielectric overlying portions of said semiconductor portion of said substrate; a first insulated gate field effect transistor comprising: a monocrystalline semiconducting channel region on a first sidewall of said dielectric, a first source/drain, and a second source/drain separated from said first source/drain along said first sidewall, in a direction substantially normal to the plane of said semiconductor portion by said channel region; a second insulated gate field effect transistor comprising: a monocrystalline semiconducting channel region on a second sidewall of said dielectric, said second sidewall opposing said first sidewall, said channel region of said first transistor being separate from said channel region of said second transistor, a first source/drain, and a second source/drain separated from said first source/drain along said second sidewall, in a direction substantially normal to the plane of said semiconductor portion by said channel region; a control gate disposed between, and capacitively coupled to control current flow in both, said first and second insulated gate field effect transistors; and a polycrystalline conducting thin film layer overlying said dielectric; wherein said polycrystalline conducting thin film layer is patterned to make contact to said respective first source/drains, and said junction-isolated diffusions in said substrate are patterned to provide contact to said second source/drains.

Claim 18

An integrated circuit device comprising: a substrate including a monocrystalline semiconductor portion including junction-isolated diffusions therein; a dielectric overlying portions of said semiconductor portion of said substrate; a first insulated gate field effect transistor comprising: a monocrystalline semiconducting channel region on a first sidewall of said dielectric, a first source/drain, and a second source/drain separated from said first source/drain along said first sidewall, in a direction substantially normal to the plane of said semiconductor portion by said channel region; a second insulated gate field effect transistor comprising: a monocrystalline semiconducting channel region on a second sidewall of said dielectric, said second sidewall opposing said first sidewall, said channel region of said first transistor being separate from said channel region of said second transistor, a first source/drain, and a second source/drain separated from said first source/drain along said second sidewall, in a direction substantially normal to the plane of said semiconductor portion by said channel region; a control gate disposed between, and capacitively coupled to control current flow in both, said first and second insulated gate field effect transistors; and a polycrystalline conducting thin film layer overlying said dielectric; wherein said polycrystalline conducting thin film layer is patterned to make contact to said respective first source/drains, and said junction-isolated diffusions in said substrate are patterned to provide contact to said second source/drains.

Claim 19

The device of claim 15, wherein said semiconductor portion of said substrate has a substantially planar surface, and said dielectric lies substantially above said planar surface.

Claim 20

The device of claim 15, wherein said polycrystalline conducting thin film layer consists essentially of a polycrystalline semiconductor material.

Claim 21

The device of claim 15, wherein said polycrystalline conducting thin film layer consists essentially of a metal.