Error limiting analog to digital converter

Claim 1

A signal amplitude indicator system having a system input at which a signal can be provided to permit providing an indication of the signal's amplitude, said system comprising: a plurality of comparators, each having a primary output and a complementary output, and each having a reference input and a signal input with each said comparator having said signal input electrically connected to said system input, and with each of said plurality of comparators providing a first set of logic values at said primary and complementary outputs if signal values occurring on said signal input sufficiently exceed a reference value present on said reference input, providing a second and opposite set of logic values at said primary and complementary outputs if signal values occurring on said signal input are less than said reference value and providing an indefinite set of logic values at said primary and complementary outputs if signal values occurring on said signal input are substantially equal to said reference value, said plurality of comparators being ordered sequentially and each successive comparator having said reference input electrically connected to one of a plurality of corresponding reference sources that each provide a reference value and are ordered by a monotonic succession of the reference values provided by each of the reference sources; a first plurality of logic gates, each of said first plurality of logic gates having first and second inputs and an output, wherein said first input of each of said first plurality of logic gates being electrically connected to said primary output of a comparator of said plurality of comparators, and said second input of each of said first plurality of logic gates being electrically connected to said complementary output of an adjacent comparator to said comparator of said plurality of said comparators in said sequence of comparators and to which said first input is electrically connected, said outputs of said first plurality of logic gates having a first code; a second plurality of logic gates, each of said second plurality of logic gates having first and second inputs and an output, wherein said first input of each of said second plurality of logic gates being electrically connected to said primary output of a comparator of said plurality of comparators, and said second input of each of said second plurality of logic gates being electrically connected to said complementary output of a comparator of said plurality of comparators that is separated from said comparator of said plurality of comparators in said sequence of comparators and to which said first input is electrically connected, said outputs of said second plurality of logic gates having a second code; and decoder means having a plurality of inputs to which said outputs of said first and second pluralities of logic gates are connected, and having a plurality of primary outputs, said decoder means providing signals at said primary outputs thereof representative of amplitudes of signals occurring on said system input based on logic states occurring at outputs of said first and second pluralities of logic gates, wherein at most one of said plurality of primary outputs is indefinite.