Patent US5070516A successfully refreshed from Google Patents.
US5070516A
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Method and apparatus for reducing noise on a signal encodable on a plurality of predetermined levels
Assignee: JS TELECOM 36-38 RUE de la PRINCESSE 78430 LOUVECIENNES - FRANCE
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Filing: 1990-03-21
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Granted: 1991-12-03
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Expires: 2010-03-21
Abstract
Abstract The invention relates to filtering a periodic digital signal having N logic levels and having noise superposed thereon. The instantaneous probability of existence of each of these logic levels is converted into a corresponding one of N signals each having its own maximum amplitude when the modulated value of the received instantaneous signal is equal to the normal value for a corresponding logic level, which amplitude falls off by application of a weighting coefficient as the received instantaneous value moves away from the normal value of that logic level. The signal relating to each looked-for logic level is integrated over the duration of an elementary modulation period in the received digital signal, and the recognized logic level is the level corresponding to the largest value integral.
Inventors
- 👤 Michel L. Le Comte
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 17:55
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4917
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
131 words
A method of filtering a received modulated digital signal having N logic levels with noise superposed thereon, N being not less than 2, wherein the instantaneous probability of existence of each logic level is converted into a corresponding one of N signals each having an amplitude which is at a maximum value when the value of the received signal is equal to the corresponding logic level and which is decreased by the application of a weighting coefficient as the value of the received signal moves away from the corresponding logic level, each of said N signals is integrated over the duration of an elementary modulation period of the received signal, and the logic level which corresponds to the largest value integral is recognized as the logic level of the received signal.
Claim 2
Independent Claim
131 words
A method of filtering a received modulated digital signal having N logic levels with noise superposed thereon, N being not less than 2, wherein the instantaneous probability of existence of each logic level is converted into a corresponding one of N signals each having an amplitude which is at a maximum value when the value of the received signal is equal to the corresponding logic level and which is decreased by the application of a weighting coefficient as the value of the received signal moves away from the corresponding logic level, each of said N signals is integrated over the duration of an elementary modulation period of the received signal, and the logic level which corresponds to the largest value integral is recognized as the logic level of the received signal.
Claim 3
Dependent Claim
53 words
A method according to claim 1, wherein the weighting coefficient varies as a function of the value of the received signal in accordance with a curve which has a maximum value when the received signal is at the corresponding logic level and which is upwardly concave on either side of that maximum value.
Claim 4
Dependent Claim
25 words
A method according to claim 1, wherein the weighting coefficient is constant over a predetermined range of received signal values embracing the corresponding logic level.
Claim 5
Dependent Claim
32 words
A method according to claim 1, wherein the weighting coefficient corresponding to a given logic level is close to a minimum value for received signal values close to a different logic level.
Claim 6
Dependent Claim
20 words
A method according to claim 1, wherein the modulation of the received signal is converted from one form to another.
Claim 7
Dependent Claim
125 words
Apparatus for implementing the method according to claim 1, the apparatus comprising: N amplitude filter paths to which the received signal is input, each path corresponding to one of said logic levels and comprising an amplifier circuit whose response curve as a function of input signal value has a maximum value when the input signal value corresponds to the corresponding logic level and a value which decreases monotonically on either side of that maximum value; an integrator circuit for integrating output signals from the amplifier circuits; and a comparator circuit for comparing the integrated signals and indicating, at the end of each elementary period of the received signal, which one of said logic levels is the most probable for the received signal over that period.
Claim 8
Dependent Claim
27 words
Apparatus according to claim 6, further including means for supplying to the amplifier circuit of each filter path a reference voltage corresponding to the corresponding logic level.
Claim 9
Dependent Claim
106 words
Apparatus according to claim 6, wherein the amplifier circuit of each filter path comprises: a first non-linear amplifier whose gain increases as the input signal value increases up to the value corresponding to the corresponding logic level; a second non-linear amplifier whose gain decreases as the input signal value increases beyond the value corresponding to the corresponding logic level; each of said first and second non-linear amplifiers having the received signal supplied to an input thereof; and a gain controlled amplifier having an input connected to an output of the first non-linear amplifier and whose gain is controlled by an output of the second non-linear amplifier.
Claim 10
Dependent Claim
24 words
Apparatus according to claim 8, wherein the reference voltage for each filter path is applied to the second non-linear amplifier of that filter path.
Claim 11
Dependent Claim
25 words
Apparatus according to claim 6, wherein the integrator circuit comprises a plurality of integrators, each being specific to a respective one of the filter paths.
Claim 12
Dependent Claim
53 words
Apparatus according to claim 6, wherein for a received signal having two logic levels, the integrator circuit comprises a single integrator common to both filter paths and actuated symmetrically in opposite directions by respective output signals of said filter paths, the comparator circuit comparing a signal from said integrator with a reference voltage.
Claim 13
Dependent Claim
61 words
Apparatus according to claim 6, further including a circuit for adding an error voltage to the received signal, said error voltage being proportional to a difference observed at the end of each elementary period between an amplitude corresponding to a recognized logic level and the actual amplitude of the received signal after HF filtering, said error voltage offsetting the received signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-12-02 | 1995-06-03 | 1995-12-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-12-02 | 1999-06-03 | 1999-12-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-12-02 | 2003-06-03 | 2003-12-03 | $7700.00 | Window Closed / Lapsed |