US5070502A
Expired / Lapsed
US
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Defect tolerant set associative cache
Assignee: Hewlett Packard Development Co LP
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Filing: 1989-06-23
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Granted: 1991-12-03
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Expires: 2009-06-23
Abstract
Abstract It is desirable to bypass the defects within a cache memory so that a high percentage of the cache is usable; otherwise the entire chip containing the cache memory must be scrapped. Since VLSI chips with a small number of defects form a large proportion of the scrapped yield, rendering chips with a small number of defects usable greatly increases the production yield and reduces the cost of each chip. Therefore, a cache memory is provided wherein each memory location includes a bit which is set in response to a detected hardware defect. Preferably, each memory location in the cache is tested by error detecting software, which sets the defect bit in any memory location containing a defect. The defect bit is tested every time data is retrieved from each memory location, and a set defect bit prohibits further use of a defective memory location.
Inventors
- 👤 Robert M. Supnik
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 11:36
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G11; G11C; G11C29/00; G11C29/70; G11C29/88; G06F2212/00; G06F2212/10; G06F2212/1032
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
76 words
A method for disabling a defective memory address location in a cache memory, comprising the steps of: a) reserving a bit in each cache memory address location; b) testing each cache memory address location for a defect; c) setting said reserved bit in a tested cache memory address location in response to a detected defect in said tested memory address location; and d) inhibiting use of any cache memory address location containing a set reserved bit.
Claim 2
Independent Claim
76 words
A method for disabling a defective memory address location in a cache memory, comprising the steps of: a) reserving a bit in each cache memory address location; b) testing each cache memory address location for a defect; c) setting said reserved bit in a tested cache memory address location in response to a detected defect in said tested memory address location; and d) inhibiting use of any cache memory address location containing a set reserved bit.
Claim 3
Dependent Claim
55 words
A method according to claim 1 wherein said step of testing includes: a) loading each bit of each cache memory address location with a binary zero; and b) comparing the contents of each cache memory address location with a preselected number to ensure that each bit of each memory address location contains a binary zero.
Claim 4
Dependent Claim
36 words
A method according to claim 2 wherein said reserved bit in a cache memory address location is set if at least one of said bits in said memory address location does not contain a binary zero.
Claim 5
Dependent Claim
53 words
A method according to claim 1 wherein said step of testing includes: a) loading each bit of each memory address location with a binary one; and b) comparing the contents of each memory address location with a preselected number to ensure that each bit of each memory address location contains a binary one.
Claim 6
Dependent Claim
35 words
A method according to claim 4 wherein said reserved bit in a memory address location is set if at least one of said bits in said memory address location does not contain a binary one.
Claim 7
Dependent Claim
52 words
A method according to claim 1 wherein said step of inhibiting includes: a) testing the status of said reserved bit in an accessed memory address location; and b) using said memory address location if said reserved bit is not set, and bypassing said memory address location if said reserved bit is set.
Claim 8
Independent Claim
116 words
A method of detecting hardware defects in a set-associative cache memory location and disabling defective cache memory locations from further use, comprising: a) reserving a bit in each cache memory location; b) testing each cache memory location for a defect; c) setting said reserved bit in a tested cache memory location in response to a detected defect in said tested cache memory location; d) inhibiting use of any cache memory location containing a set reserved bit; e) testing the status of said reserved bit in an accessed cache memory location; and f) using said cache memory location if said reserved bit is not set, and bypassing said cache memory location if said reserved bit is set.
Claim 9
Independent Claim
116 words
A method of detecting hardware defects in a set-associative cache memory location and disabling defective cache memory locations from further use, comprising: a) reserving a bit in each cache memory location; b) testing each cache memory location for a defect; c) setting said reserved bit in a tested cache memory location in response to a detected defect in said tested cache memory location; d) inhibiting use of any cache memory location containing a set reserved bit; e) testing the status of said reserved bit in an accessed cache memory location; and f) using said cache memory location if said reserved bit is not set, and bypassing said cache memory location if said reserved bit is set.
Claim 10
Dependent Claim
53 words
A method according to claim 7 wherein said step of testing includes: a) loading each bit of each cache memory location with a binary zero; and b) comparing the contents of each cache memory location with a preselected number to ensure that each bit of each cache memory location contains a binary zero.
Claim 11
Dependent Claim
35 words
A method according to claim 8 wherein said reserved bit in a cache memory location is set if at least one of said bits in said cache memory location does not contain a binary zero.
Claim 12
Dependent Claim
53 words
A method according to claim 7 wherein said step of testing includes: a) loading each bit of each cache memory location with a binary one; and b) comparing the contents of each cache memory location with a preselected number to ensure that each bit of each cache memory location contains a binary one.
Claim 13
Dependent Claim
35 words
A method according to claim 10 wherein said reserved bit in a cache memory location is set if at least one of said bits in said cache memory location does not contain a binary one.
Claim 14
Independent Claim
182 words
A method of detecting hardware defects in a cache memory location and disabling defective cache memory locations from further use, comprising: a) reserving a bit in each cache memory location; b) loading each bit of each cache memory location with a binary zero; c) comparing the contents of each cache memory location with a first preselected number to ensure that each bit of each cache memory location contains a binary zero; d) setting said reserved bit in a cache memory location if at least one of said bits in said cache memory location does not contain a binary zero; e) loading each bit of each cache memory location with a binary one; f) comparing the contents of each cache memory location with a second preselected number to ensure that each bit of each cache memory location contains a binary one; g) setting said reserved bit in a cache memory location if at least one of said bits in said cache memory location does not contain a binary one; and h) inhibiting use of any cache memory location containing a set reserved bit.
Claim 15
Independent Claim
182 words
A method of detecting hardware defects in a cache memory location and disabling defective cache memory locations from further use, comprising: a) reserving a bit in each cache memory location; b) loading each bit of each cache memory location with a binary zero; c) comparing the contents of each cache memory location with a first preselected number to ensure that each bit of each cache memory location contains a binary zero; d) setting said reserved bit in a cache memory location if at least one of said bits in said cache memory location does not contain a binary zero; e) loading each bit of each cache memory location with a binary one; f) comparing the contents of each cache memory location with a second preselected number to ensure that each bit of each cache memory location contains a binary one; g) setting said reserved bit in a cache memory location if at least one of said bits in said cache memory location does not contain a binary one; and h) inhibiting use of any cache memory location containing a set reserved bit.
Claim 16
Dependent Claim
52 words
A method according to claim 12 wherein said step of inhibiting includes: a) testing the status of said reserved bit in an accessed cache memory location; and b) using said cache memory location if said reserved bit is not set, and bypassing said cache memory location if said reserved bit is set.
Claim 17
Dependent Claim
92 words
Apparatus for disabling a defective memory address location in a cache memory, comprising: a) a cache memory having a plurality of cache memory address locations, and means for reserving a bit in each cache memory address location; b) means for testing each cache memory address location for a defect; c) means for setting said reserved bit in a tested cache memory address location in response to a detected defect in said tested memory address location; and d) means for inhibiting use of any cache memory address location containing a set reserved bit.
Claim 18
Dependent Claim
92 words
Apparatus for disabling a defective memory address location in a cache memory, comprising: a) a cache memory having a plurality of cache memory address locations, and means for reserving a bit in each cache memory address location; b) means for testing each cache memory address location for a defect; c) means for setting said reserved bit in a tested cache memory address location in response to a detected defect in said tested memory address location; and d) means for inhibiting use of any cache memory address location containing a set reserved bit.
Claim 19
Dependent Claim
58 words
Apparatus according to claim 14 wherein said means for testing includes: a) means for loading each bit of each cache memory address location with a binary zero; and b) means for comparing the contents of each cache memory address location with a preselected number to ensure that each bit of each memory address location contains a binary zero.
Claim 20
Dependent Claim
35 words
Apparatus according to claim 15 wherein said reserved bit in a cache memory address location is set if at least one of said bits in said memory address location does not contain a binary zero.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-12-02 | 1995-06-03 | 1995-12-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-12-02 | 1999-06-03 | 1999-12-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-12-02 | 2003-06-03 | 2003-12-03 | $7700.00 | Window Closed / Lapsed |