Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
319 words
A processor adapted to receive instructions and to execute multiple operations of a single instruction in parallel, comprising: an instruction latch; a main memory data port coupled to said instruction latch; an instruction decode circuit for decoding an instruction in said instruction latch coupled to said instruction latch and having a plurality of control signal outputs; a main memory address port coupled to a first one of said control signal outputs; an arithmetic logic unit having a control input coupled to a second one of said control signal outputs and a first operand input; an ALU multiplexer having an output coupled to said first operand input of said arithmetic logic unit, a first input coupled to said main memory data port via a first data path, and a select input coupled to a third one of said control signal outputs; a top register coupled to an output of said arithmetic logic unit; a next parameter register coupled to a second input of said ALU multiplexer via a second data path; an index/return register coupled to a third input of said ALU multiplexer via a third data path; a next parameter memory having a data I/O coupled to said next parameter register, said next parameter memory, next parameter register and top register forming a single parameter stack; an index/return memory having a data I/O coupled to said index/return register for storing an index/return stack; K stack pointer means having only a single pointer register for generating a pointer address for said next parameter memory having an output coupled to an address input of said next parameter memory and an input coupled to a fourth one of said control signal outputs; and a J stack pointer circuit for generating a pointer address for said index/return memory having an output coupled to an address input of said index/return memory and an input coupled to a fifth one of said control signal outputs.
Claim 2
Dependent Claim
319 words
A processor adapted to receive instructions and to execute multiple operations of a single instruction in parallel, comprising: an instruction latch; a main memory data port coupled to said instruction latch; an instruction decode circuit for decoding an instruction in said instruction latch coupled to said instruction latch and having a plurality of control signal outputs; a main memory address port coupled to a first one of said control signal outputs; an arithmetic logic unit having a control input coupled to a second one of said control signal outputs and a first operand input; an ALU multiplexer having an output coupled to said first operand input of said arithmetic logic unit, a first input coupled to said main memory data port via a first data path, and a select input coupled to a third one of said control signal outputs; a top register coupled to an output of said arithmetic logic unit; a next parameter register coupled to a second input of said ALU multiplexer via a second data path; an index/return register coupled to a third input of said ALU multiplexer via a third data path; a next parameter memory having a data I/O coupled to said next parameter register, said next parameter memory, next parameter register and top register forming a single parameter stack; an index/return memory having a data I/O coupled to said index/return register for storing an index/return stack; K stack pointer means having only a single pointer register for generating a pointer address for said next parameter memory having an output coupled to an address input of said next parameter memory and an input coupled to a fourth one of said control signal outputs; and a J stack pointer circuit for generating a pointer address for said index/return memory having an output coupled to an address input of said index/return memory and an input coupled to a fifth one of said control signal outputs.
Claim 3
Dependent Claim
62 words
The processor of claim 1 further comprising an address multiplexer having an output coupled to said main memory address port, a first input coupled to said first one of said control signal outputs, a second input coupled to said top register, a third input coupled to said index/return register and a select input coupled to a sixth one of said control signals.
Claim 4
Dependent Claim
58 words
The processor of claim 1 further comprising a main memory multiplexer having an output coupled to said main memory data port and an input of said instruction latch, a first input coupled to said top register, a second input coupled to said next parameter register and a select input coupled to a sixth one of said control signals.
Claim 5
Dependent Claim
24 words
The processor of claim 1 wherein said ALU multiplexer further includes a fourth input coupled to said first one of said control signal outputs.
Claim 6
Dependent Claim
51 words
The processor of claim 1 further comprising a next parameter multiplexer having an output coupled to said next parameter register, a first input coupled to said top register, a second input coupled to said main memory data port and a select input coupled to a sixth one of said control signals.
Claim 7
Dependent Claim
55 words
The processor of claim 1 further comprising: a program counter; and an index/return multiplexer having an output coupled to said index/return register, a first input coupled to said top register, a second input coupled to an output of said program counter and a select input coupled to a sixth one of said control signal outputs.
Claim 8
Dependent Claim
166 words
The processor of claim 1 further comprising: a fourth data path coupling an output of said top register to an input of said next parameter register; a fifth data path coupling said output of said top register to an input of said index/return register; whereby said arithmetic logic unit temporarily maintains an output value of said next parameter register while an output value of said top register is applied to an input of said next parameter register to enable a simultaneous, one clock cycle swap of the contents of top register and said next parameter register to be effected through said second and fourth data paths; and whereby said arithmetic logic unit temporarily maintains an output value of said index/return register while an output of said top register is applied to an input of said index/return register to enable a simultaneous, one clock cycle swap of the contents of said top register and said index/return register to be effected through said third and fifth data paths.
Claim 9
Dependent Claim
30 words
The processor of claim 1 further comprising means, responsive to a predetermined bit of said instructions, for performing a subroutine return operation concurrently with other operations specified by said instructions.
Claim 10
Dependent Claim
29 words
The processor of claim 1 further comprising means, responsive to a predetermined bit of said instructions, for performing a subroutine call concurrently with other operations specified by said instructions.
Claim 11
Dependent Claim
38 words
The processor of claim 9 wherein said means for performing a subroutine call comprises means for storing a program count in said index/return register and providing an output of said instruction latch to said main memory address port.
Claim 12
Dependent Claim
26 words
The processor of claim 1 further comprising means for modifying a value in one of said registers by a multi-bit literal value from said instruction latch.
Claim 13
Dependent Claim
33 words
The processor of claim 1 further comprising means for coupling said top and next registers to store a single, double-precision value and for shifting said double-precision value through said top and next registers.