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US5070383A
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Programmable memory matrix employing voltage-variable resistors
Assignee: Zoran Corp
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Filing: 1989-01-10
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Granted: 1991-12-03
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Expires: 2009-01-10
Abstract
Abstract A memory matrix comprises a plurality of word lines, a plurality of bit lines, and a stacked diode and voltage-variable resistor structure interconnecting bit lines to word lines. The stacked diode and voltage-variable resistor structure includes a doped region in a semiconductor substrate defining a work line, a doped polycrystalline silicon layer over said word line and forming a p-n junction therewith, and an amorphized region in the doped polycrystalline silicon layer having increased resistance over the non-amorphized portion of the doped polycrystalline silicon layer. A contact is made to the amorphized polycrystalline silicon material which preferably includes a titanium-tungsten barrier layer and an aluminum layer over the barrier layer. To improve the breakdown voltage of the diode structure, a region of opposite conductivity type is formed in the word line under the doped polycrystalline silicon layer either by out-diffusion of dopants from the polycrystalline silicon layer or by the implantation of dopant ions through the polycrystalline silicon layer into the word line.
Inventors
- 👤 Alexander B. Sinar
- 👤 Levy Gerzberg
- 👤 Yosef Y. Shacham
- 👤 Ilan A. Blech
- 👤 Eric R. Sirkin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:52
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/491; H10B; H10B63/00; Y; Y10; Y10S; Y10S257/00; Y10S257/91; Y10S257/926
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
101 words
A programmable memory array comprising a monocrystalline semiconductor substrate, a plurality of word lines formed in said substrate by dopants of a first conductivity type, and a plurality of stacked diode and voltage-variable resistor structures on each word line with a bit contact to each stacked diode and voltage-variable resistor, each diode comprising a doped polycrystalline layer of opposite conductivity type in contact with a word line and an ion-implanted region of opposite conductivity type in said word line thereby forming a p-n junction with said word line, and each voltage-variable resistor comprising an amorphized surface region in said polysilicon layer.
Claim 2
Dependent Claim
101 words
A programmable memory array comprising a monocrystalline semiconductor substrate, a plurality of word lines formed in said substrate by dopants of a first conductivity type, and a plurality of stacked diode and voltage-variable resistor structures on each word line with a bit contact to each stacked diode and voltage-variable resistor, each diode comprising a doped polycrystalline layer of opposite conductivity type in contact with a word line and an ion-implanted region of opposite conductivity type in said word line thereby forming a p-n junction with said word line, and each voltage-variable resistor comprising an amorphized surface region in said polysilicon layer.
Claim 3
Dependent Claim
22 words
The programmable memory array as defined by claim 1 wherein each bit contact comprises a metal contact to said amorphized surface region.
Claim 4
Dependent Claim
33 words
The programmable memory array as defined by claim 2 wherein said metal contact comprises a barrier metal layer on said amorphized surface region and a second metal layer on said barrier metal layer.
Claim 5
Dependent Claim
99 words
A stacked diode and voltage-variable resistor structure comprising a semiconductor substrate having a doped surface region of one conductivity type, a layer of doped polycrystalline silicon on said doped surface region, said doped polycrystalline silicon being of opposite conductivity type, an ion-implanted region of opposite conductivity type in said doped surface region underlying said doped polycrystalline silicon and forming a p-n junction with said doped surface region, an amorphized region in said doped polycrystalline silicon layer having higher resistance than the non-amorphized doped polycrystalline silicon layer, and a contact on said amorphized portion of said doped polycrystalline silicon layer.
Claim 6
Dependent Claim
99 words
A stacked diode and voltage-variable resistor structure comprising a semiconductor substrate having a doped surface region of one conductivity type, a layer of doped polycrystalline silicon on said doped surface region, said doped polycrystalline silicon being of opposite conductivity type, an ion-implanted region of opposite conductivity type in said doped surface region underlying said doped polycrystalline silicon and forming a p-n junction with said doped surface region, an amorphized region in said doped polycrystalline silicon layer having higher resistance than the non-amorphized doped polycrystalline silicon layer, and a contact on said amorphized portion of said doped polycrystalline silicon layer.
Claim 7
Dependent Claim
41 words
The stacked diode and voltage-variable resistor structure as defined by claim 4 wherein said contact comprises a barrier metal layer on said amorphized region of said polycrystalline silicon layer and a layer of a second metal on said barrier metal layer.
Claim 8
Dependent Claim
24 words
The stacked diode and voltage-variable resistor structure as defined by claim 5 wherein said barrier metal comprises titanium-tungsten and said second metal comprises aluminum.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-12-02 | 1995-06-03 | 1995-12-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-12-02 | 1999-06-03 | 1999-12-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-12-02 | 2003-06-03 | 2003-12-03 | $7700.00 | Window Closed / Lapsed |