Patent US5068825A successfully refreshed from Google Patents.
US5068825A
Expired / Lapsed
US
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Memory cell circuit and operation thereof
Assignee: Texas Instruments Inc
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Filing: 1990-06-29
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Granted: 1991-11-26
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Expires: 2010-06-29
Abstract
Abstract An improved memory cell 118 is provided utilizing transistor pairs 142, 144 ands 160, 162 as dual purpose transistor pairs for the two modes of operation of the cell. During the first or non-access mode of operation, the transistor pairs operate as switched capacitive elements in order to provide an equivalent resistance between bit line 140 and first node 26 and inverted bit line 158 and second node 130. Control circuit 119 maintains bit lines 140 and inverted bit line 158 high during this non-access mode. During the second or access mode of operation, each transistor pair operates as a respective pass transistor for connecting bit line 140 to first node 126 and inverted bit line 158 to second node 130 so that data may be read from, or written to, the cross-coupled transistors 120 and 122.
Inventors
- 👤 Shivaling S. Mahant-Shetti
- 👤 Mark G. Harward
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 14:49
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
112 words
A memory cell, comprising: a storage device for storing a data value; a first transistor series pair coupled to a first node of said storage device, and operable in a first mode to pull up a voltage at said first node and in a second mode to provide electrical access to said first node for read/writing said storage device; and a second transistor series pair coupled to a second node of said storage device, and operable in the first mode to pull up a voltage at said second node to a predetermined voltage level and in the second mode to provide electrical access to said second node for read/writing said storage device.
Claim 2
Dependent Claim
112 words
A memory cell, comprising: a storage device for storing a data value; a first transistor series pair coupled to a first node of said storage device, and operable in a first mode to pull up a voltage at said first node and in a second mode to provide electrical access to said first node for read/writing said storage device; and a second transistor series pair coupled to a second node of said storage device, and operable in the first mode to pull up a voltage at said second node to a predetermined voltage level and in the second mode to provide electrical access to said second node for read/writing said storage device.
Claim 3
Dependent Claim
48 words
The memory cell of claim 1 wherein said storage device comprises a cross-coupled transistor pair, wherein said first node comprises a gate of the first transistor of said cross-coupled transistor pair and wherein said second node comprises a gate of the second transistor of said cross-coupled transistor pair.
Claim 4
Dependent Claim
79 words
The memory cell of claim 1 wherein said first transistor series pair comprises: a first transistor having a source, drain and gate, said source operable to connect to a first access line and said gate operable to receive a first control signal; and a second transistor having a source, drain and gate, said source coupled to said drain of said first transistor, said gate operable to receive a second control signal and said drain coupled to said first node.
Claim 5
Dependent Claim
79 words
The memory cell of claim 3 wherein said second transistor series pair comprises: a third transistor having a source, drain and gate, said source operable to connect to a second access line and said gate operable to receive the first control signal; and a fourth transistor having a source, drain and gate, said source coupled to said drain of said third transistor, said gate operable to receive the second control signal and said drain coupled to said second node.
Claim 6
Dependent Claim
20 words
The memory cell of claim 4 wherein each of said first, second, third and fourth transistors comprise n channel transistors.
Claim 7
Dependent Claim
30 words
The memory cell of claim 1 and further comprising a clocking circuit for clocking the transistors of said first transistor series pair in a non-overlapping fashion during said first mode.
Claim 8
Dependent Claim
31 words
The memory cell of claim 6 wherein said clocking circuit is further operable to clock the transistors of said second transistor series pair in a non-overlapping fashion during said first mode.
Claim 9
Dependent Claim
32 words
The memory cell of claim 1 and further comprising a supply circuit for providing the predetermined voltage level to both of said first and second transistor series pairs during said first mode.
Claim 10
Dependent Claim
26 words
The memory cell of claim 1 and further comprising a conduct circuit for causing each of said transistor series pairs to conduct during said second mode.
Claim 11
Dependent Claim
38 words
The memory cell of claim 1 and further comprising a temperature dependent clocking circuit for clocking the transistors of said first transistor series pair and said second transistor pair at a frequency which increases with increases in temperature.
Claim 12
Dependent Claim
187 words
A memory cell, comprising: a cross-coupled transistor pair for storing a data value; a first transistor series pair coupled to a first node of said storage device, and operable in a first mode pull up a voltage at said first node by transferring a predetermined voltage level to said first node and in a second mode to provide electrical access to said first node for read/writing said storage device; a second transistor series pair coupled to a second node of said storage device, and operable in the first mode to pull up a voltage at said second node by transferring a predetermined voltage to said second node and in the second mode to provide electrical access to said second node for read/writing said storage device; and a clocking circuit for alternatively clocking the transistors of said first and second transistor pairs in a non-overlapping fashion during said first mode; a supply circuit for providing the predetermined voltage to both of said first and second transistor pairs during said first mode; and a conduct circuit for causing each of said transistor pairs to conduct during said second mode.
Claim 13
Dependent Claim
187 words
A memory cell, comprising: a cross-coupled transistor pair for storing a data value; a first transistor series pair coupled to a first node of said storage device, and operable in a first mode pull up a voltage at said first node by transferring a predetermined voltage level to said first node and in a second mode to provide electrical access to said first node for read/writing said storage device; a second transistor series pair coupled to a second node of said storage device, and operable in the first mode to pull up a voltage at said second node by transferring a predetermined voltage to said second node and in the second mode to provide electrical access to said second node for read/writing said storage device; and a clocking circuit for alternatively clocking the transistors of said first and second transistor pairs in a non-overlapping fashion during said first mode; a supply circuit for providing the predetermined voltage to both of said first and second transistor pairs during said first mode; and a conduct circuit for causing each of said transistor pairs to conduct during said second mode.
Claim 14
Dependent Claim
39 words
The memory cell of claim 11 wherein said first node comprises a gate of the first transistor of said cross-coupled transistor pair and wherein said second node comprises a gate of the second transistor of said cross-coupled transistor pair.
Claim 15
Dependent Claim
153 words
The memory cell of claim 11 wherein said first transistor series pair comprises: a first transistor having a source, drain and gate, said source operable to connect to a first access line and said gate operable to receive a first control signal; and a second transistor having a source, drain and gate, said source coupled to said drain of said first transistor, said gate operable to receive a second control signal and said drain coupled to said first node, and wherein said second transistor series pair comprises: a third transistor having a source, drain and gate, said source operable to connect to a second access line and said gate operable to receive the first control signal; and a fourth transistor having a source, drain and gate, said source coupled to said drain of said third transistor, said gate operable to receive the second control signal and said drain coupled to said second node.
Claim 16
Dependent Claim
20 words
The memory cell of claim 13 wherein each of said first, second, third and fourth transistors comprise n channel transistors.
Claim 17
Dependent Claim
40 words
The memory cell of claim 11 wherein said clocking circuit comprises a temperature dependent clocking circuit for clocking the transistors of said first transistor series pair and said second transistor pair at a frequency which increases with increases in temperature.
Claim 18
Independent Claim
115 words
A method of operating a memory cell comprising a storage device, comprising: operating a first transistor series pair coupled to a first node of the storage device in a first mode to pull up a voltage at the first node; operating the first transistor series pair in a second mode to provide electrical access to the first node for read/writing the storage device; operating a second transistor series pair coupled to a second node of the storage device in the first mode to pull up a voltage at the second node; and operating the second transistor series pair in the second mode to provide electrical access to the second node for read/writing the storage device.
Claim 19
Independent Claim
115 words
A method of operating a memory cell comprising a storage device, comprising: operating a first transistor series pair coupled to a first node of the storage device in a first mode to pull up a voltage at the first node; operating the first transistor series pair in a second mode to provide electrical access to the first node for read/writing the storage device; operating a second transistor series pair coupled to a second node of the storage device in the first mode to pull up a voltage at the second node; and operating the second transistor series pair in the second mode to provide electrical access to the second node for read/writing the storage device.
Claim 20
Dependent Claim
32 words
The method of claim 16 wherein said step of operating the first transistor series pair in the first mode comprises alternatively clocking the gates of the transistors in the first series pair.
Claim 21
Dependent Claim
32 words
The method of claim 16 wherein said step of operating the second transistor series pair in the first mode comprises alternatively clocking the gates of the transistors in the second series pair.
Claim 22
Dependent Claim
34 words
The method of claim 16 wherein said step of operating the first transistor series pair in the second mode comprises causing the transistors in the first series pair to conduct during the second mode.
Claim 23
Dependent Claim
34 words
The method of claim 16 wherein said step of operating the second transistor series pair in the second mode comprises causing the transistors in the second series pair to conduct during the second mode.
Claim 24
Dependent Claim
37 words
The method of claim 16 and further comprising supplying a predetermined voltage level to the first transistor series pair during the first mode such that the first node may be pulled up by said predetermined voltage level.
Claim 25
Dependent Claim
37 words
The method of claim 16 and further comprising supplying a predetermined voltage level to the second transistor series pair during the first mode such that the second node may be pulled up by said predetermined voltage level.
Claim 26
Dependent Claim
25 words
The method of claim 16 and further comprising clocking the first and second transistor series pairs at a frequency which increases with increases in temperature.
Claim 27
Independent Claim
149 words
A method of operating a memory cell comprising a storage device, comprising: operating a first transistor series pair coupled to a first node of the storage device in a first mode to pull up a voltage at the first node, wherein said operating step comprises alternatively clocking the gates of the transistors in the first series pair; operating the first transistor series pair in a second mode to provide electrical access to the first node for read/writing the storage device; operating a second transistor series pair coupled to a second node of the storage device in the first mode to pull up a voltage at the second node, wherein said operating step comprises alternatively clocking the gates of the transistors in the second series pair; and operating the second transistor series pair in the second mode to provide electrical access to the second node for read/writing the storage device.
Claim 28
Independent Claim
149 words
A method of operating a memory cell comprising a storage device, comprising: operating a first transistor series pair coupled to a first node of the storage device in a first mode to pull up a voltage at the first node, wherein said operating step comprises alternatively clocking the gates of the transistors in the first series pair; operating the first transistor series pair in a second mode to provide electrical access to the first node for read/writing the storage device; operating a second transistor series pair coupled to a second node of the storage device in the first mode to pull up a voltage at the second node, wherein said operating step comprises alternatively clocking the gates of the transistors in the second series pair; and operating the second transistor series pair in the second mode to provide electrical access to the second node for read/writing the storage device.
Claim 29
Dependent Claim
64 words
The method of claim 24 wherein said step of operating the first transistor series pair in the second mode comprises causing the transistors in the first series pair to conduct during the second mode, and wherein said step of operating the second transistor series pair in the second mode comprises causing the transistors in the second series pair to conduct during the second mode.
Claim 30
Dependent Claim
67 words
The method of claim 25 and further comprising: supplying a predetermined voltage level to the first transistor series pair during the first mode such that the first node may be pulled up by said predetermined voltage level; and supplying a predetermined voltage level to the second transistor series pair during the first mode such that the second node may be pulled up by said predetermined voltage level.
Claim 31
Dependent Claim
52 words
The method of claim 24 wherein said step of operating the first transistor series pair in the first mode and wherein said step of operating the second transistor series pair in the first mode comprises clocking the first and second transistor series pairs at a frequency which increases with increases in temperature.
References Cited (Backward Citations)
US4184208A
Cited
US4995001A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-11-25 | 1995-05-27 | 1995-11-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-11-25 | 1999-05-27 | 1999-11-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-11-25 | 2003-05-27 | 2003-11-26 | $7700.00 | Window Closed / Lapsed |