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US5068698A
Expired / Lapsed
US
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MOS semiconductor device having high-capacity stacked capacitor
Assignee: NEC Corp
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Filing: 1990-09-24
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Granted: 1991-11-26
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Expires: 2010-09-24
Abstract
Abstract A semiconductor memory device having a plurality of memory cells each comprising an insulated gate MOS transistor and a stacked capacitor. The stacked capacitor having a lower electrode and an oppositely disposed upper electrode whereby the lower electrode has an insulating film in its interior, thereby making it possible to increase the capacitance of the stacked capacitor without increasing the surface area of the electrode.
Inventors
- 👤 Kuniaki Koyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:44
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
65 words
A semiconductor memory device having a semiconductor substrate and a plurality of memory cells each including a stacked capacitor having a lower electrode and an oppositely disposed upper electrode, and a MOS transistor electrically connected to said lower electrode, wherein said lower electrode of said stacked capacitor has an island-shaped insulating film formed on said semiconductor substrate and a conductive layer enveloping said insulating film.
Claim 2
Dependent Claim
65 words
A semiconductor memory device having a semiconductor substrate and a plurality of memory cells each including a stacked capacitor having a lower electrode and an oppositely disposed upper electrode, and a MOS transistor electrically connected to said lower electrode, wherein said lower electrode of said stacked capacitor has an island-shaped insulating film formed on said semiconductor substrate and a conductive layer enveloping said insulating film.
Claim 3
Dependent Claim
41 words
A semiconductor memory device according to claim 1, wherein said MOS transistor is an insulated gate MOS transistor having a source and a drain, one of said source and drain being electrically connected to said lower electrode of said stacked capacitor.
Claim 4
Dependent Claim
37 words
A semiconductor memory device according to claim 1, further comprising an interlayer insulating film provided on portions other than on said capacitor, said interlayer insulating film being formed simultaneously with said insulating film of said lower electrode.
References Cited (Backward Citations)
JPH01265556A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-11-25 | 1995-05-27 | 1995-11-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-11-25 | 1999-05-27 | 1999-11-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-11-25 | 2003-05-27 | 2003-11-26 | $7700.00 | Window Closed / Lapsed |