Switched bridge circuit

Claim 2

A switched bridge circuit in which semiconductor bridge elements (T1,T2) are arranged to provide a commutated output voltage from a d.c. supply source in response to a switching signal, characterised in that a control circuit for switching the bridge elements has its output connected to a capacitor (C2) such that switching of the bridge elements (T1,T2) is prevented whilst there is a flow of current through the capacitor (C2), which is indicative of changing output voltage.

Claim 3

A circuit as claimed in claim 1, characterised in that the control circuit comprises a first transistor (T4) which has its base electrode coupled with the output its emitter electrode coupled via said capacitor (C2) to the emitter of a second transistor (T5) and its collector coupled with one of a pair of d.c. voltage supply lines (15 v) via a first resistor (R4) and a diode (D2), and to the control electrode (G) of a semiconductor element (T1) in one arm of the bridge, and in which the base of the second transistor (T5) is coupled to the other (0 V) of said pair of d.c. supply lines and the collector is coupled with the control electrode (G) of a semiconductor element (T2) in the other arm of the bridge, the collector of the first transistor is coupled via the drain/source path of a field effect transistor (T3) and a second resistor (R3) to said other d.c. supply line (OV), the gate electrode (G) of the field effect transistor (T3) is coupled to a switching signal line for receiving said switching signal which line is coupled via a third resistor (R2) with the collector of the second transistor (T5).

Claim 4

A circuit as claimed in claim 2, characterised in that the first (T4) and second (T5) transistors are each provided with a diode (D4,D5) connected between their base and emitter so as to be reverse biased when the transistor is conductive.

Claim 5

A circuit as claimed in claim 2, characterised in that a diode (T10) is connected between the emitter of the first transistor (T4) and the output and a third transistor (T11) has its base electrode coupled with the emitter electrode of the first transistor (T4) its emitter electrode coupled with the output and its collector electrode coupled with the drain of the field effect transistor.

Claim 6

A circuit as claimed in claim 2, 3 or 4, characterised in that an oscillator (11) is connected in circuit to provide the switching signal for effecting commutation.

Claim 7

A circuit as claimed in claim 5, characterised in that the collector of the first and second transistors (T4,T5) are coupled each with their different semiconductor elements in their particular arm of the bridge via a d.c. amplifier (12,13).

Claim 8

A circuit as claimed in claim 6, characterised in that the d.c. amplifiers (T12,T13) each comprise a fourth transistor (T6,T6') of one conductivity type and a fifth transistor (T7,T7') of the opposite conductivity type having their bases coupled with the collector of one of the first and second transistors (T4,T5 respectively), the emitter electrode of which fourth transistor (T6,T6') is coupled to the emitter electrode of the fifth transistor (T7,T7') and to the control electrode (G) of the semiconductor element (T1,T2) in their particular arm of the bridge and a sixth transistor(T8,T8') of said first conductivity type having its base coupled with the collector of the fifth transistor (T7,T7'), and its collector emitter path connected in parallel with one of the bridge elements (T1, T2).

Claim 9

A circuit as claimed in claim 1, characterised in that the bridge elements (T1, T2) are driven by latching circuits (22',23') which are set and reset alternately when there is no flow of current through the capacitor.

Claim 10

A circuit as claimed in claim 8, characterised in that the latches are set and reset by a logic circuit which is responsive to a control circuit in dependance upon the direction of current through the capacitor.

Claim 11

A circuit as claimed in claim 9, characterised in that the logic circuit comprises first and second NAND gates (N2, N1), the first NAND gate (N2) has a first input coupled with an input for the switching signal, a second input connected with the control circuit and an output coupled with the set or reset input of a first one of the latching circuits (22'), the other reset or set input of the first latching circuit is connected with the input via an inverter, the second NAND gate has a first input coupled via an inverter (I31) with the input for the switching signal a second input connected with the control circuit and an output coupled with the set or reset input of the second one of the latching circuits (23') and the other reset or set input of the second latching circuit is connected with the inverted switching signal via a further inverter.

Claim 12

A circuit as claimed in claim 10, characterised in that the circuit between the input for the switching signal and the set input of each latching circuit (22', 23') includes delay means (I32, I33, I34, I35).

Claim 13

A circuit as claimed in claim 11, characterised in that the delay means comprises one or more inverter circuits.

Claim 14

A circuit as claimed in any one of claims 10 to 12, characterised in that the circuit between the input for the switching signal and each of the set and reset inputs of the latching circuits (22', 23') includes a differentiating circuit.

Claim 15

A circuit as claimed in claim 13, characterised in that the control circuit comprises a first transistor (T21) of one polarity type which has its emitter electrode coupled via the capacitor (C2') to the bridge output, its collector electrode coupled to one logic voltage line (0 V), its base electrode coupled to its emitter electrode via a resistor and also to the emitter of a second transistor (T22) of said one polarity type the base electrode of which is coupled to said one logic voltage line and the collector of which is coupled via a resistor to a second logic voltage line (5 V) and provides a first output indicative of direction of current through the capacitor (C2'), a third transistor (T23) of opposite polarity type which has its collector electrode coupled to said one logic voltage line (0 V) its base electrode coupled to said one logic voltage line (0 V) by a diode (T24) and its emitter electrode coupled to the bridge output via the capacitor C2' and also to the base electrode of a fourth transistor (T26) of said one polarity type via a resistor (R23) the base electrode of the fourth transistor is coupled with said one logic voltage line via a diode (T25) and the collector electrode of the fourth transistor (T26) is coupled via a resistor (R24) to said second logic voltage line (5 V) and provides a second output indicative of direction of current through the capacitor (C2'), the output of which second and fourth transistors are each coupled to the second input of a different one of the NAND gates (N1, N2).

Claim 16

A circuit as claimed in claim 14, characterised in that the inputs of the latching circuits (23', 22') which are coupled with the output of the first and second NAND gates (N2, N1) are preceeded by an inverter (I36, I39) whilst the other inputs to the latching circuits are coupled via third and fourth dual input NAND gates (N4, N3), the other input of which third and fourth gates are coupled with the output of a different one of said second and fourth transistors (T22, T26).

Claim 17

A circuit as claimed in claim 15, characterised in that each of the first and second NAND gates (N2, N1) has a third input which is coupled to the input for the switching signal, the first of which NAND gates (N2) is coupled therewith via the inverter (I31).

Claim 18

A circuit as claimed in claim 16, characterised in that each of the NAND gates (N2, N1) has a fourth input which is coupled with said circuit between the input for the switching signal and the set input of the latching means of the other NAND gate (N1, N2).

Claim 19

A circuit as claimed in claim 14, characterised in that the set and reset inputs of the latching circuits (23', 22') are each preceded by an inverter (I36, I37, I38, I39).

Claim 20

A circuit as claimed in claim 18, characterised in that it is fabricated on a single integrated circuit chip.

Claim 21

An a.c. powered switched bridge circuit, characterised in the combination of a voltage clamp (21) coupled in parallel with a pair of input lines for a source of alternating current supply, a rectifier circuit (22) coupled with the output of the voltage clamp and a switched bridge circuit (20) as claimed in any one of the preceding claims coupled with the output of the rectifier circuit.

Claim 22

A fluorescent lamp unit, characterised in the combination of a fluorescent tube (10) and ballast and an a.c. powered switched bridge circuit as claimed in claim 20 the bridge circuit of which is configured as a switched mode power converter which feeds the tube and ballast.

Claim 23

A fluorescent lamp unit as claimed in claim 21, characterised in that the voltage clamp (21), the rectifier circuit (22), the switched bridge circuit (20), the tube (10) and ballast are all incorporated in a housing.

Claim 24

A fluorescent lamp unit as claimed in claim 22, characterised in that the voltage clamp (21), the rectifier circuit (23) the switched bridge circuit (20) and the ballast are all incorporated in a luminaire for receiving a miniature fluorescent tube (10).

Claim 25

A fluorescent lamp unit as claimed in claim 23, characterised in that the lamp unit is adapted for removeable connection to a lamp socket such as is suitable for connection of an incandescent light bulb.