Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
249 words
A signal processing circuit of a bar code reader, comprising: signal input means for optically detecting a bar code provided on a surface of goods and outputting a first signal after optical-to-electrical conversion; differential means, connected to said signal input means, for amplifying the first signal, differentiating the first signal, filtering the first signal after differentiation to eliminate a high frequency noise, and outputting a second signal after filtering; comparison means, connected to said differential means, for integrating the second signal and outputting a third signal after integration, and comparing the second signal with the third signal and outputting a fourth signal when the third signal is larger than the second signal; slice level generation means, connected to said differential means, for holding a peak voltage of the second signal, suppressing the peak voltage to a predetermined upper limitation voltage, discharging the suppressed peak voltage in accordance with a predetermined time constant, and dividing the suppressed peak voltage into a predetermined voltage rate to obtain a positive slice voltage and aa negative slice voltage; gate signal output means, connected to said differential means and said slice level generation means, for comparing the second signal with the positive slice voltage and the negative slice voltage; and signal output means, connected to said comparison means and said gate signal output means, for inputting the fourth signal and the positive slice voltage, inputting the inverted fourth signal and the negative slice voltage, and outputting a gate signal to obtain a binary-coded signal.
Claim 2
Dependent Claim
249 words
A signal processing circuit of a bar code reader, comprising: signal input means for optically detecting a bar code provided on a surface of goods and outputting a first signal after optical-to-electrical conversion; differential means, connected to said signal input means, for amplifying the first signal, differentiating the first signal, filtering the first signal after differentiation to eliminate a high frequency noise, and outputting a second signal after filtering; comparison means, connected to said differential means, for integrating the second signal and outputting a third signal after integration, and comparing the second signal with the third signal and outputting a fourth signal when the third signal is larger than the second signal; slice level generation means, connected to said differential means, for holding a peak voltage of the second signal, suppressing the peak voltage to a predetermined upper limitation voltage, discharging the suppressed peak voltage in accordance with a predetermined time constant, and dividing the suppressed peak voltage into a predetermined voltage rate to obtain a positive slice voltage and aa negative slice voltage; gate signal output means, connected to said differential means and said slice level generation means, for comparing the second signal with the positive slice voltage and the negative slice voltage; and signal output means, connected to said comparison means and said gate signal output means, for inputting the fourth signal and the positive slice voltage, inputting the inverted fourth signal and the negative slice voltage, and outputting a gate signal to obtain a binary-coded signal.
Claim 3
Dependent Claim
92 words
A signal processing circuit as claimed in claim 1, wherein said slice level generation means comprises: a peak hold circuit for receiving the second signal and holding the peak voltage of the second signal; an upper limitation circuit connected to said peak hold circuit for receiving an output of said peak hold circuit and suppressing the peak voltage to the predetermined upper limitation voltage; and a discharge circuit connected to said upper limitation circuit for discharging the peak voltage suppressed by said upper limitation circuit in accordance with the predetermined time constant.
Claim 4
Dependent Claim
24 words
A signal processing circuit as claimed in claim 1, wherein the predetermined voltage rate is determined to be half of the upper limitation voltage.
Claim 5
Dependent Claim
43 words
A signal processing circuit as claimed in claim 2, wherein said upper limitation circuit comprises: an operational amplifier to reduce the peak voltage when the peak voltage exceeds the predetermined upper limitation voltage; and a variable resistor to determine the upper limitation voltage.
Claim 6
Dependent Claim
54 words
A signal processing circuit according to claim 1, wherein said slice level generation means comprises: a peak hold circuit; an upper limitation circuit connected to said peak hold circuit; a discharge circuit connected to said upper limitation circuit; and a voltage division circuit connected between said discharge circuit and said gate signal output means.