Candidate selection processor

Claim 2

A processor for selecting potentially valid code signals supplied by a coded label scanner which serially scans nonoriented coded labels and provides a continuous multilevel signal having at least two levels corresponding to the coded information on the label, said coded label having a plurality of encoded characters each of which includes a plurality of abutting substantially rectangular bars of differing characteristics, said bars for each of said characters having substantially the same total width in the direction of information content and at least one additional character having at least as many bars as the aforesaid characters and in which the total width of a number of bars equal to the number of bars in each of the aforesaid characters is of substantially different total width in the direction of information content comprising: first means connected to said scanner for storing an epoch of the signal corresponding to the potentially valid code to be selected from amongst the signals received from the scanner; second means responsive to the signals from said scanner for forming electric signals, for each of the character phases, which correspond to the total width of the character in the direction of information content; third means for comparing substantially simultaneously for each of said character phases of the signal, the total width in the direction of information content of successive characters and encoding at least two predetermined relationships; fourth means for substantially simultaneously examining the encoded relationships and providing output signals whenever the said encoded relationships have a predetermined format; and fifth means responsive to the output signals provided by said fourth means for gating the then stored epoch of the signal in the first means to a utilization device.

Claim 3

The processor set forth in claim 1 in which the number of phases phi equals the number of bars psi used to encode each of the characters and each of the phases phi 1- phi n for an n bar coded character coincide in time with the transitIon occurring when the leading edge of the bars psi 1- psi n are detected by the scanner in a repetitive sequence.

Claim 4

The processor set forth in claim 2 in which the signal supplied by the said scanner is substantially a square wave signal which the scanner generates when scanning the coded label with a substantially constant velocity to provide a square wave signal corresponding to the bar coded label and said first means includes: circuit means for providing control signals coincident with the transitions of the square wave signal supplied by the scanner; a fixed frequency oscillator for providing electric signals at a fixed predetermined frequency; and counter means responsive to the control signals from said circuit means and said electric signals from fixed frequency oscillator for providing a count signal corresponding to the elapsed time between transitions of said square wave signal from the scanner which signals are stored under control of said control signals by said first means.

Claim 5

The processor set forth in claim 3 in which said second means includes: clock signal generating means responsive to the said circuit means and said fixed frequency oscillator for continuously providing n clocking signals each synchronized with n sequential transitions of the said control signals, and n counter means each responsive to the fixed frequency oscillator and a different one of said n clocking signals for accumulating a count between successive clocking signals which corresponds to the length of a character in the direction of information content, and n register means each responsive to one of said n counter means and the aforesaid associated clocking signals for storing the count attained by the said connected counter under control of the aforesaid associated clocking signals.

Claim 6

The processor set forth in claim 4 in which said third means includes: n processing channels each connected to one of said n register means and each responsive to the aforesaid associated clocking signals for receiving and storing the contents of the connected register means under control of the aforesaid associated clocking signals and for comparing the said stored contents with the contents of the connected register means under control of the aforesaid clocking signals to encode and register at least two predetermined relationships of the contents compared.

Claim 7

A processor for selecting potentially valid code signals supplied by a coded label scanner which serially scans non-oriented coded labels supported on containers or the like and provides a continuous multilevel signal having at least two levels corresponding to the coded information on the label, said coded label having a plurality of optically encoded characters each of which includes a plurality of abutting substantially rectangular bars of differing light reflectivity, said bars for each of said characters having substantially the same total width in the direction of information content and at least one additional character having at least as many bars as the aforesaid characters and in which the total width of a number of bars equal to the number of bars in each of the aforesaid characters is of substantially different total width in the direction of information content comprising: first means connected to said scanner for modifying the form of the signal supplied by said scanner and storing an epoch of the modified signal corresponding to the potentially valid code to be selected from amongst the signals received from the scanner; second means responsive to the modified signals from said scanner for forming electric signals, for each of the character phases, which correspond to the total width of the character in the direction of information content; third means for comparing substantially simultaneously for each of the said character phases of the modified signal, the total width in the direction of information content of succeSsive characters and encoding and storing one of at least two predetermined relationships based on the results of the comparison; fourth means for substantially simultaneously examining the encoded stored relationships and providing output signals whenever the said encoded relationships have a predetermined format; and fifth means responsive to the output signals provided by said fourth means for gating the then stored epoch of the modified signal in the first means to a utilization device.

Claim 8

A processor for selecting potentially valid code signals supplied by a coded label scanner which serially scans non-oriented coded labels supported on containers or the like and provides a continuous multilevel signal having at least two levels corresponding to the coded information on the label, said coded label having a plurality of optically encoded characters each of which includes a plurality of abutting substantially rectangular bars of differing light reflectivity, said bars for each of said characters having substantially the same total width in the direction of information content and at least one additional character having at least as many bars as the aforesaid characters and in which the total width of a number of bars equal to the number of bars in each of the aforesaid characters is of substantially different total width in the direction of information content comprising: first means connected to said scanner for modifying the form of the signal supplied by said scanner and storing an epoch of the modified signal corresponding to the potentially valid code to be selected from amongst the signals received from the scanner; second means responsive to the modified signals from said scanner for forming electric signals, for each of the character phases, which correspond to the total width of the character in the direction of information content; third means for comparing substantially simultaneously for each of the said character phases of the modified signal, the total width in the direction of information content of succeSsive characters and encoding and storing one of at least two predetermined relationships based on the results of the comparison; fourth means for substantially simultaneously examining the encoded stored relationships and providing output signals whenever the said encoded relationships have a predetermined format; and fifth means responsive to the output signals provided by said fourth means for gating the then stored epoch of the modified signal in the first means to a utilization device.

Claim 9

The processor set forth in claim 6 in which the number of phases phi equals the number of bars psi used to encode each of the characters and each of the phases phi 1- phi 4 for a four bar coded character coincide in time with the transition occurring when the leading edge of the bars psi 1-psi 4 are detected by the scanner in a repetitive sequence.

Claim 10

The processor set forth in claim 7 in which the signal supplied by the said scanner is substantially a square wave signal which the scanner generates when scanning the coded label with a substantially constant velocity to provide a square wave signal corresponding to the bar coded label and said first means includes: circuit means for providing control signals coincident with the transitions of the square wave signal supplied by the scanner; a fixed frequency oscillator for providing electric signals at a fixed predetermined frequency; and counter means responsive to the control signals from said circuit means and said electric signals from fixed frequency oscillator for providing a count signal corresponding to the elapsed time between transitions of said square wave signal from the scanner which signals are stored under control of said control signals by said first means.

Claim 11

The processor set forth in claim 8 in which said second means includes: clock signal generating means responsive to the said circuit means and said fixed frequency oscillator for continuously providing four clocking signals each synchronized with four sequential transitions of the control signals, and four counter means each responsive to the fixed frequency oscillator and a different one of said four clocking signals for accumulating a count between successive clocking signals which corresponds to the length of a character in the direction of information content, and four register means each responsive to one of said four counter means and the aforesaid associated clocking signals for storing the count attained by the said connected counter under control of the aforesaid associated clocking signals.

Claim 12

The processor set forth in claim 9 in which said third means includes: four processing channels each connected to one of said four register means and each responsive to the aforesaid associated clocking signals for receiving and storing the contents of the connected register means under control of the aforesaid associated clocking signals and for comparing the said stored contents with the contents of the connected register means under control of the aforesaid clocking signals to encode and register at least two predetermined relationships of the contents compared.