Global reset and zero detection for a memory system

Claim 1

A memory system having a global reset capability, comprising: (MEMORY ARRAY) a memory array having an array of memory cells arranged in rows and columns; (TAG COLUMN) tag bit storage means, having one tag-memory cell associated with each row of memory cells, each of said tag-memory cells having a zero state, which is indicative of all of the data information stored in the memory cells of an associated row actually being in the zero state or which is alternatively indicative of all of the data information being stored in the memory cells of an associated row being treated as being in the zero state, each of said tag-memory cells having a one state, which is indicative that at least one of the memory cells of an associated row contains data information in a non-zero state; (INPUT DATA ZERO DETECT LOGIC) detection means for detecting that input data signals to a row of memory cells are all zeroes, said detection means including means for providing an output signal indicative of all zero input to said row of memory cells; (RESET LINE) means for resetting a tag-memory cell to a zero state to indicate that the data information stored in the associated row is actually or is to be treated as containing all zeros, independent of the actual state of the data information being stored in the associated row of memory cells, thereby providing a global reset function for the entire array of memory cells without having to individually reset the data information stored in the array of memory cells.