Patent US5067091A successfully refreshed from Google Patents.
US5067091A
Expired / Lapsed
US
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Circuit design conversion apparatus
Assignee: Toshiba Corp
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Filing: 1989-01-19
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Granted: 1991-11-19
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Expires: 2009-01-19
Abstract
Abstract A circuit design conversion apparatus comprises hierarchical circuit data memory, hierarchical structure analyzer, hierarchical structure data memory, conversion module register, conversion rule memory, conversion module table memory, conversion control unit, module pick-up unit, circuit design conversion unit and conversion rule remake unit. Circuit connection data which hierarchically described the connection of an LSI is input to the hierarchial circuit data memory. Hierarchical structure analyzer analyzes the circuit structure to obtain a hierarchical structure data, which in turn is stored in the hierarchical structure data memory. The name of a module, to be scan designed, is initially registered in the conversion rule memory. Considering the hierarchical structure data and the conversion rule the name of a module higher in level than the module registered in the conversion rule is registered in conversion module table memory which includes a pointer for representing a modules to be scan designed next. Conversion control unit supplies, to module pick-up unit, the name of a module which is pointed by a pointer. Module pick-up unit picks up circuit connection data, relating to that module, from the hierarchical circuit data memory, and supplies it to circuit design conversion unit to convert into a scan design relating to that module.
Inventors
- 👤 Masahisa Nakazawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 18:09
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318583; G06; G06F; G06F30/00; G06F30/30; G06F11/00; G06F11/22; G06F11/2205; G06F11/2236
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
169 words
A circuit design conversion apparatus responsive to circuit connection data representing connection between modules of a circuit with an hierarchical structure, hierarchical structure data representing the hierarchical structure of the circuit, and a conversion rule indicating a scannable module of the circuit, comprising: means for providing a conversion module table representing modules higher in level than the scannable module indicated by the conversion rule, in accordance with the hierarchical structure data and the conversion rule, the table including a pointer indicating the module to be scan-design-converted; circuit design converting means for converting the circuit connection data of the module indicated by the pointer of said conversion module table into a scannable design; and updating means for adding the name of the module which is scan-design-converted into said conversion rule, adding the name of the module higher in level than the module which is scan-design-converted into said conversion module table, and shifting the pointer of said conversion module table in accordance with the name of the module which is scan-design-converted.
Claim 2
Dependent Claim
169 words
A circuit design conversion apparatus responsive to circuit connection data representing connection between modules of a circuit with an hierarchical structure, hierarchical structure data representing the hierarchical structure of the circuit, and a conversion rule indicating a scannable module of the circuit, comprising: means for providing a conversion module table representing modules higher in level than the scannable module indicated by the conversion rule, in accordance with the hierarchical structure data and the conversion rule, the table including a pointer indicating the module to be scan-design-converted; circuit design converting means for converting the circuit connection data of the module indicated by the pointer of said conversion module table into a scannable design; and updating means for adding the name of the module which is scan-design-converted into said conversion rule, adding the name of the module higher in level than the module which is scan-design-converted into said conversion module table, and shifting the pointer of said conversion module table in accordance with the name of the module which is scan-design-converted.
Claim 3
Dependent Claim
37 words
An apparatus according to claim 1, in which said circuit design converting means includes means for replacing modules in the conversion module table by scannable modules and means for connecting the scannable modules by a scan path.
Claim 4
Dependent Claim
65 words
An apparatus according to claim 1, in which said circuit design converting means includes means for connecting scan clock buffers in a tree-like fashion to the scannable modules such that an equal number of stages of scan clock buffers are connected to each of the scannable modules and that a substantially equal number of scannable modules are connected to each of the scan clock buffers.
Claim 5
Dependent Claim
28 words
An apparatus according to claim 3, in which said circuit design converting means includes means for connecting scan clock buffers of a respective stage within a respective module.
Claim 6
Dependent Claim
27 words
An apparatus according to claim 3, in which said circuit design converting means includes means for connecting scan clock buffers of all stages within a highest module.
Claim 7
Dependent Claim
48 words
The converter according to claim 1, in which said circuit design converting means includes means for detecting an asynchronous node within the module and means for inserting a gate to the detected asynchronous node, one input of the gate being connected to an external input of the module.
Claim 8
Independent Claim
255 words
An apparatus for converting into a scan design a circuit design of a circuit including modules formed of a combinational logic circuit and a register, the modules being a scannable module and nonscannable module, said apparatus comprising: means for inputting a circuit design of the circuit representing connection of modules with a hierarchical structure and names of the scannable modules; means for analyzing the circuit design input by said inputting means, to detect the hierarchical structure; module table means for storing names of the modules of which the circuit design is converted into the scan design, in accordance with the names of the scannable modules input by said inputting means, the module table means having a pointer for representing the name of the module of which the circuit design is to be converted into the scan design next; circuit design converting means for selecting the circuit design of the module represented by the pointer of said module table means from the circuit design input by said inputting means, and converting the circuit design of the selected module into the scan design by interconnecting the scannable modules by a scan path; and control means for registering in said module table means a name of a module higher in level than the module of which the circuit design is converted into the scan design by said circuit design converting means, shifting the pointer in said modules table means, and stopping circuit design conversion by said circuit design converting means when the pointer does not represent any module.
Claim 9
Independent Claim
255 words
An apparatus for converting into a scan design a circuit design of a circuit including modules formed of a combinational logic circuit and a register, the modules being a scannable module and nonscannable module, said apparatus comprising: means for inputting a circuit design of the circuit representing connection of modules with a hierarchical structure and names of the scannable modules; means for analyzing the circuit design input by said inputting means, to detect the hierarchical structure; module table means for storing names of the modules of which the circuit design is converted into the scan design, in accordance with the names of the scannable modules input by said inputting means, the module table means having a pointer for representing the name of the module of which the circuit design is to be converted into the scan design next; circuit design converting means for selecting the circuit design of the module represented by the pointer of said module table means from the circuit design input by said inputting means, and converting the circuit design of the selected module into the scan design by interconnecting the scannable modules by a scan path; and control means for registering in said module table means a name of a module higher in level than the module of which the circuit design is converted into the scan design by said circuit design converting means, shifting the pointer in said modules table means, and stopping circuit design conversion by said circuit design converting means when the pointer does not represent any module.
Claim 10
Dependent Claim
30 words
An apparatus according to claim 7, in which a module higher than a module containing a scannable module within said circuit design is initially set to said module table means.
Claim 11
Dependent Claim
91 words
An apparatus according to claim 7, in which said control means further comprises a conversion rule memory for registering a name of a module of modules in said circuit data in which a scan design has already converted, in which the name of said module after the conversion into the scan design circuit thereof is registered in a conversion rule memory and, upon the reference of the registered name of a module in said rule memory, a module higher in level than said module is registered in said module table means.
Claim 12
Dependent Claim
37 words
An apparatus according to claim 7, in which said circuit design converting means includes means for replacing modules in the conversion module table by scannable modules and means for connecting the scannable modules by a scan path.
Claim 13
Dependent Claim
69 words
An apparatus according to claim 7, in which said circuit design converting means includes means for connecting a greater number of scan clock buffers in a tree-like fashion to the scannable modules such that an equal number of stages of scan clock buffers are connected to each of the scannable modules and that a substantially equal number of scannable modules are connected to each of the scan clock buffers.
Claim 14
Dependent Claim
28 words
An apparatus according to claim 11, in which said circuit design converting means includes means for connecting scan clock buffers of a respective stage within a respective module.
Claim 15
Dependent Claim
27 words
An apparatus according to claim 11, in which said circuit design converting means includes means for connecting scan clock buffers of all stages within a highest module.
Claim 16
Dependent Claim
48 words
An apparatus according to claim 7, in which said circuit design converting means includes means for detecting an asynchronous node within the module and means for inserting a gate to the detected asynchronous node, one input of the gate being connected to an external input of the module.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-11-18 | 1995-05-20 | 1995-11-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-11-18 | 1999-05-20 | 1999-11-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-11-18 | 2003-05-20 | 2003-11-19 | $7700.00 | Window Closed / Lapsed |