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US5067006A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Sumitomo Electric Industries Ltd
•
Filing: 1990-08-15
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Granted: 1991-11-19
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Expires: 2010-08-15
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Abstract

Abstract The device includes an insulating substrate and first and second conducting patterns, electrically insulated from another, formed on the substrate. The second conducting pattern is connected to ground. A semiconductor chip is die-bonded to the first conducting pattern. The chip has a reception circuit, including a capacitor, formed therein, and a metal film is formed on a back surface of the chip. The capacitor includes a first terminal and a second terminal, with one of the first terminal and the second terminal being electrically connected to the first conducting pattern, such that the electric potential of the capacitor is transmitted to the metal film formed on the back surface of the chip. A buffer amplifier is interposed between the one of the first terminal and the second terminal which is electrically connected to the first conducting pattern such that the potential of the capacitor is transmitted to the metal film through the buffer amplifier. The first and second terminals constitute parallel electrode patterns forming the capacitor.

Inventors

  • 👤 Nobuo Shiga

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 15:12
CPC Classifications
H; H10; H10W; H10W44/00; H10W44/601; H10F; H10F30/00; H10F77/00; H10F77/10; H10F77/12; H10F77/124; H10F77/1248; H10W20/00; H10W20/40; H10W20/41; H10W20/427; H10W70/00; H10W70/60; H10W70/62; H10W70/65; H10W72/00; H10W72/50; H10W72/541; H10W72/5449; H10W90/00; H10W90/701; H10W90/751; H10W90/754; Y; Y10; Y10S; Y10S257/00; Y10S257/916

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 129 words
A semiconductor device comprising: an insulating substrate; a first conducting pattern and a second conducting patter formed on said substrate, said first conducting pattern and said second conducting pattern being electrically insulated from each other and said second conducting pattern being connected to ground; and a semiconductor chip having (a) a reception circuit formed therein, said reception circuit including a capacitor, and (b) a metal film formed on a back surface of said chip, said chip being die-bonded on said first conducting pattern, said capacitor being formed in said chip and including a first terminal and a second terminal, one of said first terminal and said second terminal being electrically connected to said first conducting pattern, whereby an electrical potential of said capacitor is transmitted to said metal film.
Claim 2
Dependent Claim 129 words
A semiconductor device comprising: an insulating substrate; a first conducting pattern and a second conducting patter formed on said substrate, said first conducting pattern and said second conducting pattern being electrically insulated from each other and said second conducting pattern being connected to ground; and a semiconductor chip having (a) a reception circuit formed therein, said reception circuit including a capacitor, and (b) a metal film formed on a back surface of said chip, said chip being die-bonded on said first conducting pattern, said capacitor being formed in said chip and including a first terminal and a second terminal, one of said first terminal and said second terminal being electrically connected to said first conducting pattern, whereby an electrical potential of said capacitor is transmitted to said metal film.
Claim 3
Dependent Claim 40 words
A semiconductor device as in claim 1, wherein a buffer amplifier is interposed between said one of said first terminal and said second terminal, and the potential of said capacitor is transmitted to said metal film through said buffer amplifier.
Claim 4
Dependent Claim 22 words
A semiconductor device as in claim 1, wherein said first terminal and said second terminal constitute parallel electrode patterns forming said capacitor.

References Cited (Backward Citations)

US4266239A Cited
US4788584A Cited
US4617586A Cited
US4952795A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1994-11-18 1995-05-20 1995-11-19 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1998-11-18 1999-05-20 1999-11-19 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2002-11-18 2003-05-20 2003-11-19 $7700.00 Window Closed / Lapsed

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