Semiconductor device having improved high frequency characteristics

Claim 2

A semiconductor device comprising: an insulator substrate having a major surface; first, second and third metal layers disposed on said major surface of said insulator substrate and mutually separated from each other, said first metal layer serving as an input terminal, said second metal layer serving as an output terminal, and said third metal layer serving as a common terminal; a semiconductor chip having a bottom surface and an upper surface and bonded at said bottom surface on said second metal layer, the upper surface of said semiconductor chip including an input electrode and a common electrode. a first bonding wire connected at one end to said first metal layer and at its other end to said input electrode of said semiconductor chip; a second bonding wire connected at one end to said third metal layer and at its other end to said common electrode of said semiconductor chip; a piece of conductive metal covering said first and second bonding wires, said semiconductor chip, and the smallest space between said first and second metal layers; a supporting member mechanically supporting said piece of conductive metal in a manner such that said piece of conductive metal is spaced from said bonding wires and from said semiconductor chip; means for supplying a fixed potential to said piece of conductive metal; and a molded resin enclosing said piece of conductive metal, said semiconductor chip, and said bonding wires and attached to said piece of conductive metal and to at least a portion of said major surface of said insulator substrate.

Claim 3

The semiconductor device as set forth in claim 1, in which said supporting member is mechanically and electrically connected to said piece of conductive metal and to said third metal layer.

Claim 4

The semiconductor device as set forth in claim 1, in which said first metal layer and said second metal layer are formed substantially in a line and the smallest space between said first and second metal layers exists on said line.

Claim 5

The semiconductor device as set forth in claim 1, further comprising first, second, and third external leads having end portions respectively mechanically and electrically connected to said first, second, and third metal layers, said end portions of said external leads being enclosed with said molded resin.

Claim 6

The semiconductor device as set forth in claim 1, in which an output electrode is formed on said bottom surface of said semiconductor chip and mechanically and electrically connected to said second metal layer.

Claim 7

A semiconductor device comprising: an insulator substrate having a major surface; first, second, third, and fourth metal layers disposed on said major surface of said insulator substrate and mutually separated from each other, said first and second metal layers being formed substantially in a line, said third and fourth metal layers being disposed on opposite sides of said line, said first metal layer serving as an input terminal, said second metal layer serving as an output terminal, and said third and fourth metal layers serving as common terminals. a semiconductor chip having a bottom surface and an upper surface and bonded at said bottom surface onto said second metal layer, said semiconductor chip having an input and a common electrode at said upper surface, a smallest space being formed on said major surface of said insulator substrate between said first metal layer and said semiconductor chip; a conductive bridge member bridging from said third metal layer to said fourth metal layer across said line and mechanically and electrically connected to said third and fourth metal layers, said bridge member being separated from said first and second metal layers; a first bonding wire connected at one end to said first metal layer and at its other end to said input electrode of said semiconductor chip, and separated from said major surface under said smallest space across said smallest space; a second bonding wire connected at one end to said bridge member and at its other end to said common electrode of said semiconductor chip; a shielding metal plate covering said first and second bonding wires, said semiconductor chip, said bridge member, and said smallest space on said major surface of said insulator substrate; means for supplying said shielding metal plate with a voltage of a fixed potential; a first supporting member mechanically and electrically connected to said shielding metal plate and to said third metal layer and supporting said shielding metal plate in a manner such that said shielding metal plate is spaced from said bonding wires, from said semiconductor chip, from said bridge member, and from said smallest space; means for electrically connecting said fourth metal layer to said shielding metal plate; first, second, third, and fourth external metal leads mechanically and electrically connected at their peripheral portions to said first, second, third, and fourth metal layers, respectively; a molded resin enclosing said shielding metal plate, said bonding wires, said semiconductor chip, and said peripheral portions of said first, second, third, and fourth external metal leads, and attached to said shielding metal plate and to at least a portion of said major surface of said insulator substrate.

Claim 8

A semiconductor device comprising: an insulator substrate having a major surface; first, second, third, and fourth metal layers disposed on said major surface of said insulator substrate and mutually separated from each other, said first and second metal layers being formed substantially in a line, said third and fourth metal layers being disposed on opposite sides of said line, said first metal layer serving as an input terminal, said second metal layer serving as an output terminal, and said third and fourth metal layers serving as common terminals. a semiconductor chip having a bottom surface and an upper surface and bonded at said bottom surface onto said second metal layer, said semiconductor chip having an input and a common electrode at said upper surface, a smallest space being formed on said major surface of said insulator substrate between said first metal layer and said semiconductor chip; a conductive bridge member bridging from said third metal layer to said fourth metal layer across said line and mechanically and electrically connected to said third and fourth metal layers, said bridge member being separated from said first and second metal layers; a first bonding wire connected at one end to said first metal layer and at its other end to said input electrode of said semiconductor chip, and separated from said major surface under said smallest space across said smallest space; a second bonding wire connected at one end to said bridge member and at its other end to said common electrode of said semiconductor chip; a shielding metal plate covering said first and second bonding wires, said semiconductor chip, said bridge member, and said smallest space on said major surface of said insulator substrate; means for supplying said shielding metal plate with a voltage of a fixed potential; a first supporting member mechanically and electrically connected to said shielding metal plate and to said third metal layer and supporting said shielding metal plate in a manner such that said shielding metal plate is spaced from said bonding wires, from said semiconductor chip, from said bridge member, and from said smallest space; means for electrically connecting said fourth metal layer to said shielding metal plate; first, second, third, and fourth external metal leads mechanically and electrically connected at their peripheral portions to said first, second, third, and fourth metal layers, respectively; a molded resin enclosing said shielding metal plate, said bonding wires, said semiconductor chip, and said peripheral portions of said first, second, third, and fourth external metal leads, and attached to said shielding metal plate and to at least a portion of said major surface of said insulator substrate.

Claim 9

The semiconductor device as set forth in claim 6, in which an output electrode is formed on said bottom surface of said semiconductor chip, and mechanically and electrically connected to said second metal layer.

Claim 10

A semiconductor device comprising: an insulator base plate having a major surface; base, collector, and emitter metal layers disposed on said major surface and mutually separated from each other, said base and collector metal layers being formed substantially in a line, said base metal layer serving as an input terminal, said collector metal layer serving as an output terminal, and said emitter metal layer serving as a common terminal; a transistor element having base and emitter electrodes at its upper surface and a collector electrode at its bottom surface, said collector electrode being mechanically and electrically connected to said collector metal layer; a collector coupling wire connected at one end to said base metal layer and at its other end to said base electrode of said transistor element across a space between said base metal layer and said collector metal layer, and separated from said major surface between said base and collector metal layers; an emitter coupling wire electrically coupling said emitter metal layer to said emitter electrode of said transistor element. a metal plate covering said emitter and collector coupling wires, said transistor element, and said space without mechanically touching them; a supporting metal connected at one end to said emitter metal layer and at its other end to said metal plate, and supporting said metal plate in a manner such that said metal plate is separated from said bonding wires and from said transistor element; base, emitter, and collector external leads mechanically and electrically connected at one end portion to said base, emitter, and collector metal layers, respectively; and a molded resin encapsulating said metal plate, said transistor element, and said coupling wires and adhering to said metal plate and to at least one part of said major surface of said base plate.

Claim 11

A semiconductor device comprising: an insulator base plate having a major surface; base, collector, and emitter metal layers disposed on said major surface and mutually separated from each other, said base and collector metal layers being formed substantially in a line, said base metal layer serving as an input terminal, said collector metal layer serving as an output terminal, and said emitter metal layer serving as a common terminal; a transistor element having base and emitter electrodes at its upper surface and a collector electrode at its bottom surface, said collector electrode being mechanically and electrically connected to said collector metal layer; a collector coupling wire connected at one end to said base metal layer and at its other end to said base electrode of said transistor element across a space between said base metal layer and said collector metal layer, and separated from said major surface between said base and collector metal layers; an emitter coupling wire electrically coupling said emitter metal layer to said emitter electrode of said transistor element. a metal plate covering said emitter and collector coupling wires, said transistor element, and said space without mechanically touching them; a supporting metal connected at one end to said emitter metal layer and at its other end to said metal plate, and supporting said metal plate in a manner such that said metal plate is separated from said bonding wires and from said transistor element; base, emitter, and collector external leads mechanically and electrically connected at one end portion to said base, emitter, and collector metal layers, respectively; and a molded resin encapsulating said metal plate, said transistor element, and said coupling wires and adhering to said metal plate and to at least one part of said major surface of said base plate.

Claim 12

The semiconductor device as set forth in claim 8, in which said emitter coupling wire is electrically and mechanically connected at one end to said emitter metal layer and at its other end to said emitter electrode of said transistor element.

Claim 13

The semiconductor device as set forth in claim 8, further comprising a collector electrode at said bottom surface of said transistor element, and means for electrically and mechanically connecting said collector electrode to said collector metal layer.

Claim 14

The semiconductor device as set forth in claim 8, wherein said emitter metal layer includes first and second parts positioned on opposite sides of said line formed by said base and collector metal layers.

Claim 15

The semiconductor device as set forth in claim 11, further comprising an electrical coupling bridge mechanically and electrically connected to said first and second parts of said emitter metal layer, and a bonding wire connected at one end to said emitter electrode of said transistor element and at its other end to said coupling bridge.