Patent US5066608A successfully refreshed from Google Patents.
US5066608A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making a DRAM cell with stacked trench capacitor
Assignee: Samsung Electronics Co Ltd
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Filing: 1990-03-16
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Granted: 1991-11-19
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Expires: 2010-03-16
Abstract
Abstract A semiconductor device and a manufacturing method therefor are disclosed, the semiconductor device including a field oxide layer selectively formed on a semiconductor substrate for defining an active region; an electrically insulated gate electrode; a source and a drain region; a trench formed in the semiconductor substrate; an impurity-doped region formed at the surface of the trench; a first insulating layer; a second conductive layer; a dielectric film; a third conductive layer; a fourth conductive layer; an etch blocking layer; a fifth conductive layer. The manufacturing method comprises a plurality of processes for forming the above mentioned parts by applying various processes. According to the present invention, as both the impurity-doped polycrystalline silicon layer of the upper portion of the transistor and the inside of the trench including the impurity-doped region are simultaneously used as the first electrode of the capacitor, the surface area of the capacitor electrode can be made larger.
Inventors
- 👤 Seong-tae Kim
- 👤 Su-han Choi
- 👤 Jae-hong Ko
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 16:32
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/37; H10B12/377; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10B12/0387; H10B12/033
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
213 words
A method of manufacturing a semiconductor device, comprising the steps of: growing a field oxide layer on a semiconductor substrate of a first conductivity type to define an active region; forming a first insulating layer on the sample obtained after forming a gate electrode of a first conductive layer, a source region and a drain region on said active region; forming an opening to expose a part of said source region; forming a first electrode pattern by depositing a second polycrystalline silicon layer on said first insulating layer and the entire surface of the exposes substrate; forming a mask by depositing a second insulating layer on said first electrode pattern; forming a trench in said semiconductor substrate within said source region by applying said mask; doping impurities on both said first electrode pattern and said semiconductor substrate of inside of said trench, such that said first impurity-doped electrode patterns is in direct contact with impurity-doped region formed on inside of said trench; forming a dielectric film on both said impurity-doped first electrode pattern and said inside of said trench including said impurity-doped region; depositing a third conductive layer, an etch blocking layer and a fourth conductive layer onto said dielectric film in turn; and depositing a fifth conductive layer after a planarization step.
Claim 2
Independent Claim
213 words
A method of manufacturing a semiconductor device, comprising the steps of: growing a field oxide layer on a semiconductor substrate of a first conductivity type to define an active region; forming a first insulating layer on the sample obtained after forming a gate electrode of a first conductive layer, a source region and a drain region on said active region; forming an opening to expose a part of said source region; forming a first electrode pattern by depositing a second polycrystalline silicon layer on said first insulating layer and the entire surface of the exposes substrate; forming a mask by depositing a second insulating layer on said first electrode pattern; forming a trench in said semiconductor substrate within said source region by applying said mask; doping impurities on both said first electrode pattern and said semiconductor substrate of inside of said trench, such that said first impurity-doped electrode patterns is in direct contact with impurity-doped region formed on inside of said trench; forming a dielectric film on both said impurity-doped first electrode pattern and said inside of said trench including said impurity-doped region; depositing a third conductive layer, an etch blocking layer and a fourth conductive layer onto said dielectric film in turn; and depositing a fifth conductive layer after a planarization step.
Claim 3
Dependent Claim
39 words
The manufacturing method for a semiconductor device as claimed in claim 1, wherein said opening to expose a part of said source region is formed by etching said first insulating layer through a wet or a wet-dry combined etching.
Claim 4
Dependent Claim
40 words
The manufacturing method for a semiconductor device as claimed in claim 2, wherein said first insulating layer is etched larger than the dimension of the photoresist pattern used in forming said opening to expose a part of said source region.
Claim 5
Dependent Claim
28 words
The manufacturing method for a semiconductor device as claimed in claim 1, wherein said second insulating layer is made of a low or a high temperature oxide layer.
Claim 6
Dependent Claim
51 words
The manufacturing method for a semiconductor device as claimed in claim 1, wherein a dimension of said mask of said step of forming a mask is same as or smaller than a critical dimension of said photoresist pattern used in forming said opening to expose a part of said source region.
Claim 7
Dependent Claim
39 words
The manufacturing method for a semiconductor device as claimed in claim 1, wherein after forming said trench, said mask is used as a seed for growing a sacrificial oxide layer to round the sharp corner region of said trench.
Claim 8
Dependent Claim
27 words
The manufacturing method for a semiconductor device as claimed in claim 1, wherein said step of doping impurities includes a diffusion technique or an ion implantation technique.
Claim 9
Dependent Claim
62 words
The manufacturing method for a semiconductor device as claimed in claim 1, wherein said step of forming a dielectric film includes forming a first oxide layer on both said second conductive layer and said inside of said trench including said impurity-doped region, forming a nitride oxide layer on said first oxide layer, and forming a second oxide layer on said nitride layer.
Claim 10
Dependent Claim
28 words
The manufacturing method for a semiconductor device as claimed in claim 8, wherein said first oxide layer is made of a high or a low temperature oxide layer.
Claim 11
Dependent Claim
28 words
The manufacturing method for a semiconductor device as claimed in claim 1, wherein said etch blocking layer is made of a low or a high temperature oxide layer.
Claim 12
Dependent Claim
21 words
The manufacturing method for a semiconductor device as claimed in claim 1, wherein said planarization is formed by an etchback technique.
Claim 13
Dependent Claim
28 words
The manufacturing method for a semiconductor device as claimed in claim 11, wherein said etch blocking layer exposed through the said planarization is removed by buffered oxide etch.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-11-18 | 1995-05-20 | 1995-11-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-11-18 | 1999-05-20 | 1999-11-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-11-18 | 2003-05-20 | 2003-11-19 | $7700.00 | Window Closed / Lapsed |