Divide apparatus employing multiplier with overlapped partial quotients

Claim 2

A divide apparatus comprising: means for determining an approximate reciprocal M of a divisor D 0 in dependence on given higher bits of the divisor D 0 ; multiplying means for multiplying a dividend N 0 by the approximate reciprocal M to derive a quotient; wherein said multiplying means comprises: means for executing the following reiterative calculations: A=1-D.sub.0 ×M Q.sub.1 +N.sub.1 =N.sub.0 ×M Q.sub.i +N.sub.i =A×Q.sub.i-1 +N.sub.i-1 (i≧2) where A denotes a coefficient used as a factor used as a multiplicand of Q i-1 when Q i is calculated therefrom, Q i denotes a partial quotient, and N i denotes a number obtained by subtracting Q i from an (i-1)-th partial remainder multiplied by M; means for executing the following calculation: Q.sub.LAST+1 +N.sub.LAST+1 =A×(Q.sub.LAST +L)+N.sub.LAST where Q LAST denotes a last partial quotient, and L denotes a number having a magnitude corresponding to a lowest bit of the last partial quotient Q LAST ; a plurality of multiple generators for scanning multipliers for multiplicands thereby to generate multiples of said multiplicands; a plurality of carry-save adders connected to the multiple generators and having tree structures for outputting a partial sum and a partial carry; a carry propagate adder connected to the carry-save adders for adding the partial sum and the partial carry; means for feeding the partial sum and the partial carry to the multiple generators as a multiplier with respect to the partial quotient Q i-1 ; and means for inputting the partial sum and the partial carry into the carry-save adders with respect to the number N i-1 ; the divide apparatus further including: means connected to said multiplying means for storing the respective partial quotients Q 1 , Q 2 , . . . , Q LAST ; and means for calculating a final quotient Q* from the partial quotients by reference to the following equation: Q*=Q.sub.1 +Q.sub.2 +. . . +Q.sub.LAST +Y(the highest bit of Q.sub.LAST+1) and for outputting the final quotient Q*.

Claim 3

A divide apparatus comprising: means for determining an approximate reciprocal M of a divisor D 0 in dependence on given higher bits of the divisor D 0 ; multiplying means for multiplying a dividend N 0 by the approximate reciprocal M to derive a quotient; wherein said multiplying means comprises: means for executing the following reiterative calculations: A=1-D.sub.0 ×M Q.sub.1 +N.sub.1 =N.sub.0 ×M Q.sub.i +N.sub.i =A×Q.sub.i-1 +N.sub.i-1 (i≧2) where A denotes a coefficient used as a factor used as a multiplicand of Q i-1 when Q i is calculated therefrom, Q i denotes a partial quotient, and N i denotes a number obtained by subtracting Q i from an (i-l)-th partial remainder multiplied by M; means for executing the following calculation: Q.sub.LAST+1 +N.sub.LAST+1 =A×(Q.sub.LAST +L)+N.sub.LAST where Q LAST denotes a last partial quotient, and L denotes a number having a magnitude corresponding to a lowest bit of the last partial quotient Q LAST ; multiplying devices, whose number is equal to a number of times of multiplication, for executing reiterative calculations; a first multiplying unit for calculating a product of the divisor D 0 and the approximate reciprocal M; a second multiplying unit for calculating a product of the dividend N 0 and the approximate reciprocal M, wherein the first and second multiplying units are arranged in parallel, and wherein the multiplying devices are arranged in series with the first and second multiplying units; and a plurality of registers connected between the multiplying devices and the first and second multiplying units for providing synchronization among the multiplying devices and the first and second multiplying units; the divide apparatus further including: means connected to said multiplying means for storing the respective partial quotients Q 1 , Q 2 , . . . , Q LAST ; and means for calculating a final quotient Q* from the partial quotients by reference to the following equation: Q*=Q.sub.1 +Q.sub.2 +. . . +Q.sub.LAST +Y(the highest bit of Q.sub.LAST+1) and for outputting the final quotient Q*; and a plurality of delay registers for delaying and storing the number A in synchronism with the reiterative calculations.

Claim 4

A divide apparatus comprising: means for determining an approximate reciprocal M of a divisor D 0 in dependence on given higher bits of the divisor D 0 ; multiplying means for multiplying a dividend N 0 by the approximate reciprocal M to derive a quotient; wherein said multiplying means comprises: means for executing the following reiterative calculations: A=1-D.sub.0 ×M Q.sub.1 +N.sub.1 =N.sub.0 ×M Q.sub.i +N.sub.i =A×Q.sub.i-1 +N.sub.i-1 (i≧2) where A denotes a coefficient used as a factor used as a multiplicand of Q i-1 when Q i is calculated therefrom, Q i denotes a partial quotient, and N i denotes a number obtained by subtracting Q i from an (i-l)-th partial remainder multiplied by M; means for executing the following calculation: Q.sub.LAST+1 +N.sub.LAST+1 =A×(Q.sub.LAST +L)+N.sub.LAST where Q LAST denotes a last partial quotient, and L denotes a number having a magnitude corresponding to a lowest bit of the last partial quotient Q LAST ; multiplying devices, whose number is equal to a number of times of multiplication, for executing reiterative calculations; a first multiplying unit for calculating a product of the divisor D 0 and the approximate reciprocal M; a second multiplying unit for calculating a product of the dividend N 0 and the approximate reciprocal M, wherein the first and second multiplying units are arranged in parallel, and wherein the multiplying devices are arranged in series with the first and second multiplying units; and a plurality of registers connected between the multiplying devices and the first and second multiplying units for providing synchronization among the multiplying devices and the first and second multiplying units; the divide apparatus further including: means connected to said multiplying means for storing the respective partial quotients Q 1 , Q 2 , . . . , Q LAST ; and means for calculating a final quotient Q* from the partial quotients by reference to the following equation: Q*=Q.sub.1 +Q.sub.2 +. . . +Q.sub.LAST +Y(the highest bit of Q.sub.LAST+1) and for outputting the final quotient Q*; and a plurality of delay registers for delaying and storing the number A in synchronism with the reiterative calculations.

Claim 5

A divide apparatus comprising: means for determining an approximate reciprocal M of a divisor D 0 in dependence on given higher bits of the divisor D 0 ; multiplying means for multiplying a dividend N 0 by the approximate reciprocal M to derive a quotient; wherein said multiplying means comprises: means for executing the following reiterative calculations: A=1-D.sub.0 ×M Q.sub.1 +N.sub.1 =N.sub.0 ×M Q.sub.i +N.sub.i =A×Q.sub.i-1 +N.sub.i-1 (i≧2) where A denotes a coefficient used as a factor used as a multiplicand of Q i-1 when Q i is calculated therefrom, Q i denotes a partial quotient, and N i denotes a number obtained by subtracting Q i from an (i-1)-th partial remainder multiplied by M; means for executing the following calculation: Q.sub.LAST+1 +N.sub.LAST+1 =A×(Q.sub.LAST +L)+N.sub.LAST where Q LAST denotes a last partial quotient, and L denotes a number having a magnitude corresponding to a lowest bit of the last partial quotient Q LAST ; multiplying devices, whose number is equal to a number of times of multiplication, for executing reiterative calculations; a first multiplying unit for calculating a product of the divisor D 0 and a two's complement of the approximate reciprocal M; a second multiplying unit for calculating a product of the dividend N 0 and the approximate reciprocal M, wherein the first and second multiplying units are arranged in parallel, and wherein the multiplying devices are arranged in series with the first and second multiplying units; and a plurality of registers connected between the multiplying devices and the first and second multiplying units for providing synchronization among the multiplying devices and the first and second multiplying units; the divide apparatus further including: means connected to said multiplying means for storing the respective partial quotients Q 1 , Q 2 , . . . , Q LAST ; and means for calculating a final quotient Q* from the partial quotients by reference to the following equation: Q*=Q.sub.1 +Q.sub.2 +. . . +Q.sub.LAST +Y(the highest bit of Q.sub.LAST+1) and for outputting the final quotient Q*; and a plurality of delay registers for delaying and storing the number A in synchronism with the reiterative calculations.

Claim 6

A divide apparatus comprising: means for determining an approximate reciprocal M of a divisor D 0 in dependence on given higher bits of the divisor D 0 ; multiplying means for multiplying a dividend N 0 by the approximate reciprocal M to derive a quotient; wherein said multiplying means comprises: means for executing the following reiterative calculations: A=1-D.sub.0 ×M Q.sub.1 +N.sub.1 =N.sub.0 ×M Q.sub.i +N.sub.i =A×Q.sub.i-1 +N.sub.i-1 (i≧2) where A denotes a coefficient used as a factor used as a multiplicand of Q i-1 when Q i is calculated therefrom, Q i denotes a partial quotient, and N i denotes a number obtained by subtracting Q i from an (i-1)-th partial remainder multiplied by M; means for executing the following calculation: Q.sub.LAST+1 +N.sub.LAST+1 =A×(Q.sub.LAST +L)+N.sub.LAST where Q LAST denotes a last partial quotient, and L denotes a number having a magnitude corresponding to a lowest bit of the last partial quotient Q LAST ; multiplying devices, whose number is equal to a number of times of multiplication, for executing reiterative calculations; a first multiplying unit for calculating a product of the divisor D 0 and a two's complement of the approximate reciprocal M; a second multiplying unit for calculating a product of the dividend N 0 and the approximate reciprocal M, wherein the first and second multiplying units are arranged in parallel, and wherein the multiplying devices are arranged in series with the first and second multiplying units; and a plurality of registers connected between the multiplying devices and the first and second multiplying units for providing synchronization among the multiplying devices and the first and second multiplying units; the divide apparatus further including: means connected to said multiplying means for storing the respective partial quotients Q 1 , Q 2 , . . . , Q LAST ; and means for calculating a final quotient Q* from the partial quotients by reference to the following equation: Q*=Q.sub.1 +Q.sub.2 +. . . +Q.sub.LAST +Y(the highest bit of Q.sub.LAST+1) and for outputting the final quotient Q*; and a plurality of delay registers for delaying and storing the number A in synchronism with the reiterative calculations.