US5063575A — Apparatus and method for proper byte alignment in…

Claim 1

Independent Claim 170 words

In an Encoder/Decoder (ENDEC) receiver utilized in a Fiber Distributed Data Interface (FDDI) network, said receiver including a first in-first out (FIFO) memory, and a serial to parallel shifter for receiving data information from other nodes within the network; an apparatus for ensuring that the data information received from other nodes is accurately decoded without generating a fragment byte, comprising: means for detecting a first predetermined signal received in said shifter from another node in the network, said predetermined signal indicating that said another node is idle; and logic for controlling the writing of data information into said FIFO memory, wherein said logic disables writing of received data information to said FIFO memory in response to an output signal from the detecting means indicating that said predetermined signal has been detected, and wherein said logic enables writing of received data information to said FIFO memory in response to receipt of a second predetermined signal in said shifter, thereby providing for the transmission of said data information from said ENDEC receiver.

Claim 2

Dependent Claim 170 words

In an Encoder/Decoder (ENDEC) receiver utilized in a Fiber Distributed Data Interface (FDDI) network, said receiver including a first in-first out (FIFO) memory, and a serial to parallel shifter for receiving data information from other nodes within the network; an apparatus for ensuring that the data information received from other nodes is accurately decoded without generating a fragment byte, comprising: means for detecting a first predetermined signal received in said shifter from another node in the network, said predetermined signal indicating that said another node is idle; and logic for controlling the writing of data information into said FIFO memory, wherein said logic disables writing of received data information to said FIFO memory in response to an output signal from the detecting means indicating that said predetermined signal has been detected, and wherein said logic enables writing of received data information to said FIFO memory in response to receipt of a second predetermined signal in said shifter, thereby providing for the transmission of said data information from said ENDEC receiver.

Claim 3

Dependent Claim 25 words

The apparatus of claim 1 in which said detecting means comprises a circuit for recognizing the first predetermined signal in the serial to parallel shifter.

Claim 4

Dependent Claim 23 words

The apparatus of claim 1 in which said logic comprises a write disable circuit connected to selectively enable and disable the FIFO memory.

Claim 5

Dependent Claim 27 words

The apparatus of claim 1 in which said logic comprises means for detecting said second predetermined signal in an output from said serial to parallel shifter means.

Claim 6

Dependent Claim 136 words

In an Encoder/Decoder (ENDEC) receiver utilized in a Fiber Distributed Data Interface (FDDI) network, said receiver including a first in-first out (FIFO) memory, and a serial to parallel shifter for receiving data information from other nodes within the network; a method for ensuring that the data information received from other nodes is accurately decoded comprising the steps of: (a) detecting a first predetermined signal received in said shifter from another node in the network, said predetermined signal indicating that said another node is idle; (b) disabling writing of received data information to said FIFO memory when said first predetermined signal is detected; and (c) writing received data information into said FIFO memory upon detection of a second predetermined signal received in said shifter, thereby providing for the transmission of said data information from said ENDEC receiver.

Claim 7

Dependent Claim 136 words

In an Encoder/Decoder (ENDEC) receiver utilized in a Fiber Distributed Data Interface (FDDI) network, said receiver including a first in-first out (FIFO) memory, and a serial to parallel shifter for receiving data information from other nodes within the network; a method for ensuring that the data information received from other nodes is accurately decoded comprising the steps of: (a) detecting a first predetermined signal received in said shifter from another node in the network, said predetermined signal indicating that said another node is idle; (b) disabling writing of received data information to said FIFO memory when said first predetermined signal is detected; and (c) writing received data information into said FIFO memory upon detection of a second predetermined signal received in said shifter, thereby providing for the transmission of said data information from said ENDEC receiver.

Claim 8

Dependent Claim 160 words

An Encoder/Decoder (ENDEC) receiver which can be utilized in a Fiber distributed Interface (FDDI) network comprising: a shift register for changing serially received data to parallel data; means for decoding said parallel data; a first in-first out (FIFO) memory for receiving the decoded parallel data, the FIFO memory having a plurality of levels for receiving said decoded parallel data; means for detecting a first predetermined signal, in said shift register, received from another node in the network, said first predetermined signal indicating that said another node is idle; means for disabling writing of data to said FIFO memory when said first predetermined signal is detected by the detecting means; means for enabling writing of said decoded parallel data to said FIFO memory upon receipt of a second predetermined signal by said shift register; and means for receiving said decoded parallel data from said FIFO memory wherein said receiving means provides said parallel data to another portion of the FDDI network.

Claim 9

Dependent Claim 160 words

An Encoder/Decoder (ENDEC) receiver which can be utilized in a Fiber distributed Interface (FDDI) network comprising: a shift register for changing serially received data to parallel data; means for decoding said parallel data; a first in-first out (FIFO) memory for receiving the decoded parallel data, the FIFO memory having a plurality of levels for receiving said decoded parallel data; means for detecting a first predetermined signal, in said shift register, received from another node in the network, said first predetermined signal indicating that said another node is idle; means for disabling writing of data to said FIFO memory when said first predetermined signal is detected by the detecting means; means for enabling writing of said decoded parallel data to said FIFO memory upon receipt of a second predetermined signal by said shift register; and means for receiving said decoded parallel data from said FIFO memory wherein said receiving means provides said parallel data to another portion of the FDDI network.

Claim 10

Dependent Claim 36 words

The ENDEC receiver of claim 6 in which said detecting means comprises a gate circuit in said shift register for detecting said first predetermined signal and outputting a signal from said shift register in response thereto.

Claim 11

Dependent Claim 26 words

The ENDEC receiver of claim 7 in which the disabling means comprises a write disable circuit which is responsive to said signal from said shift register.

Claim 12

Dependent Claim 22 words

The ENDEC receiver of claim 8 in which the enabling means operate responsive to a second predetermined signal from said shift register.

Claim 13

Dependent Claim 131 words

In an Encoder/Decoder (ENDEC) receiver in a node of a data communication network, an apparatus for ensuring that data received from other network nodes is accurately decoded without generating a fragment byte, said apparatus comprising: first detecting means for detecting receipt of a first predetermined data signal from another network node; second detecting means for detecting receipt of a second predetermined data signal from said another network node; and a logic circuit for controlling writing of received data within said receiver, wherein said logic circuit disables writing of received data in response to the detection of said first predetermined data signal by said first detecting means, and said logic circuit enables writing of received data in response to the detection of said second predetermined data signal by said second detecting means.

Claim 14

Dependent Claim 131 words

In an Encoder/Decoder (ENDEC) receiver in a node of a data communication network, an apparatus for ensuring that data received from other network nodes is accurately decoded without generating a fragment byte, said apparatus comprising: first detecting means for detecting receipt of a first predetermined data signal from another network node; second detecting means for detecting receipt of a second predetermined data signal from said another network node; and a logic circuit for controlling writing of received data within said receiver, wherein said logic circuit disables writing of received data in response to the detection of said first predetermined data signal by said first detecting means, and said logic circuit enables writing of received data in response to the detection of said second predetermined data signal by said second detecting means.

Claim 15

Dependent Claim 53 words

An apparatus as claimed in claim 10, wherein said first detecting means comprises a serial to parallel shift register which receives data signals from said other network nodes, said shift register producing an output to said logic circuit when data comprising said second predetermined data signal has been shifted into said shift register.

Claim 16

Dependent Claim 38 words

An apparatus as claimed in claim 11, wherein said first detecting means comprises a gate circuit responsive to data in said shift register, said gate circuit detecting receipt of the first predetermined data signal in said shift register.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1994-11-04	1995-05-06	1995-11-05	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1998-11-04	1999-05-06	1999-11-05	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2002-11-04	2003-05-06	2003-11-05	$7700.00	Window Closed / Lapsed

Apparatus and method for proper byte alignment in an encoder/decoder

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