US5063456A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Video signal processor
Assignee: Hitachi Ltd
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Filing: 1989-08-03
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Granted: 1991-11-05
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Expires: 2009-08-03
Abstract
Abstract A video signal processor suitable for use with a VTR, the processor being provided with a circuit for eliminating inserted information signals other than a time code at a stage prior to the addition of a time code signal to the vertical blanking period of a video signal, providing accurate time code reading in a VTR equipped with a circuit for recording or reproducing the time code signal.
Inventors
- 👤 Tadasu Horiuchi
- 👤 Hideo Nishijima
- 👤 Shoji Ohno
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 13:16
CPC Classifications
H; H04; H04N; H04N9/00; H04N9/79; H04N9/80; H04N9/82; H04N9/8205; H04N9/8233; G; G11; G11B; G11B27/00; G11B27/10; G11B27/19; G11B27/28; G11B27/30; G11B27/3027; G11B27/3036; G11B27/3054; G11B2220/00; G11B2220/90
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
353 words
A video signal processor comprising: an input terminal connected to receive a video signal; a Y/C separator for separating the video signal received at the input terminal into a luminance signal and a chrominance signal and for outputting the luminance signal and the chrominance signal; a sync signal separator connected to the Y/C separator for extracting a synchronizing signal from the luminance signal output by the Y/C separator; a blanking processor connected to receive a first control signal and the luminance signal output by said Y/C separator; a time code generator connected to receive a second control signal for generating a time code; a controller which is responsive to the synchronizing signal extracted by said sync signal separator for outputting the first control signal for controlling said blanking processor and the second control signal for controlling said time code generator, said controller controlling said blanking processor by way of the first control signal so that said blanking processor removes information signals other than the synchronizing signal from the luminance signal inserted in a vertical blanking period of the received video signal, and further for controlling said time code generator by way of the second control signal so that the time code generated by said time code generator is inserted in the luminance signal from which the information signals have been removed; a time code mix circuit connected to receive the time code generated by said time code generator and the luminance signal from which the information signals have been removed from said blanking processor for mixing the time code and the luminance signal from which the information signals have been removed, said time code mix circuit outputting a mixed signal resulting from the mixing of the time code and the luminance signal from which the information signals have been removed; signal processing means for converting the mixed signal and the chrominance signal into signals suitable for recording, respectively, and for outputting the signals suitable for recording; and means for amplifying at least one of the signals suitable for recording output by said signal processing means prior to recording said at least one signal.
Claim 2
Dependent Claim
353 words
A video signal processor comprising: an input terminal connected to receive a video signal; a Y/C separator for separating the video signal received at the input terminal into a luminance signal and a chrominance signal and for outputting the luminance signal and the chrominance signal; a sync signal separator connected to the Y/C separator for extracting a synchronizing signal from the luminance signal output by the Y/C separator; a blanking processor connected to receive a first control signal and the luminance signal output by said Y/C separator; a time code generator connected to receive a second control signal for generating a time code; a controller which is responsive to the synchronizing signal extracted by said sync signal separator for outputting the first control signal for controlling said blanking processor and the second control signal for controlling said time code generator, said controller controlling said blanking processor by way of the first control signal so that said blanking processor removes information signals other than the synchronizing signal from the luminance signal inserted in a vertical blanking period of the received video signal, and further for controlling said time code generator by way of the second control signal so that the time code generated by said time code generator is inserted in the luminance signal from which the information signals have been removed; a time code mix circuit connected to receive the time code generated by said time code generator and the luminance signal from which the information signals have been removed from said blanking processor for mixing the time code and the luminance signal from which the information signals have been removed, said time code mix circuit outputting a mixed signal resulting from the mixing of the time code and the luminance signal from which the information signals have been removed; signal processing means for converting the mixed signal and the chrominance signal into signals suitable for recording, respectively, and for outputting the signals suitable for recording; and means for amplifying at least one of the signals suitable for recording output by said signal processing means prior to recording said at least one signal.
Claim 3
Dependent Claim
79 words
A video signal processor as claimed in claim 1, wherein a time code reader responsive to the first control signal from the controller for reading a time code from the luminance signal output by said Y/C separator is provide at a stage prior to said time code mix circuit and the time code generator generates the same time code as that read by the time code reader upon the reading of the time code by said time code reader.
Claim 4
Dependent Claim
119 words
A video signal processor as claimed in claim 1, wherein said controller comprises a counter connected to the sync signal separator so that said counter is initialized by a vertical synchronizing signal output from said sync signal separator and thereafter counts a horizontal synchronizing signal from said sync signal separator, decode pulse generating means responsive to said counter for generating decode pulses at an initial timing and an end timing of the vertical blanking period and at a position where the horizontal synchronizing signal corresponds to the time code generated by said time code generator, and a control signal generator responsive to the decode pulses from said decode pulse generating means for generating the first and second control signals.
References Cited (Backward Citations)
US3996610A
Cited
US4167759A
Cited
US4419699A
Cited
US4517598A
Cited
US4737862A
Cited
US4786978A
Cited
US4802023A
Cited
US4908722A
Cited
US4870297A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-11-04 | 1995-05-06 | 1995-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-11-04 | 1999-05-06 | 1999-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-11-04 | 2003-05-06 | 2003-11-05 | $7700.00 | Window Closed / Lapsed |