Semiconductor integrated circuit device having standard cells including internal wiring region

Claim 2

A semiconductor integrated device comprising: a plurality of standard cell rows extending in a first direction, each row including first standard cells; a wiring region, which is arranged between two adjacent ones of said standard cell rows and in which cell connection wirings are formed; wherein at least one said standard cell row includes at least one second standard cell; and said at least one second standard cell contains an internal wiring region containing a cell connection wiring arranged in said first direction and having two ends, one of said two ends being coupled to one of the wirings formed in said wiring region, and the other of said two ends being coupled to another of the wirings formed in said wiring region; said second cell contains a positive power source line region in which a positive power source line is formed; and said second cell contains a negative power source line region in which a negative power source line is formed.

Claim 3

A semiconductor integrated circuitu device according to claim 1, wherein said internal wiring region is arranged between said positive and negative power source line regions and the cell connection wiring formed in said internal wiring region is arranged in parallel with said positive and negative power source lines.

Claim 4

A semiconductor integrated circuit device according to claim 1, wherein said at least one second standard cell further includes a circuitu element region in which a logic gate is formed; said positive and negative power source lines being connected to the logic gate formed in said circuit element region; and the cell connection wiring formed in said internal wiring region being arranged parallel to said positive and negative power source lines.

Claim 5

A semiconductor integrated circuitu device comprising: a plurality of standard cell rows extending in a first direction, each row including first standard cells; a plurality of wiring regions, each of which is situated between adjacent said standard cell rows, and in each of which cell connection wirings are formed; wherein at least one said standard cell row includes at least one second standard cell; and said at least one second standard cell contains a circuit element region in which a logic gate is formed; said second cell contains a positive power source line region in which is formed a positive power source line for supplying a positive power source potential to the logic gate formed in said circuitu element region; said second cell contains a negative power source line region in which is formed a negative power source line for supplying a negative power source potential to the logic gate formed in said circuit element region; said second cell contains a first internal wiring region containing a first cell connection wiring arranged in said first direction and having two ends, said two ends of said first cell connection wiring being respectively coupled to separate wirings formed in one of two of said adjacent wiring regions, said at least one standard cell row including said second cell being located between said two wiring regions, said first internal wiring region being situated between said positive power source line region and said circuit element region; and said second cell contains a second internal wiring region containing a second cell connection wiring arranged in said first direction and having two ends, said two ends of said second cell connection wiring being respectively coupled to separate wirings formed in the other of said two wiring regions, said second internal wiring region being situated between said negative power source line region and said circuitu element region.

Claim 6

A semiconductor integrated circuitu device comprising: a plurality of standard cell rows extending in a first direction, each row including first standard cells; a plurality of wiring regions, each of which is situated between adjacent said standard cell rows, and in each of which cell connection wirings are formed; wherein at least one said standard cell row includes at least one second standard cell; and said at least one second standard cell contains a circuit element region in which a logic gate is formed; said second cell contains a positive power source line region in which is formed a positive power source line for supplying a positive power source potential to the logic gate formed in said circuitu element region; said second cell contains a negative power source line region in which is formed a negative power source line for supplying a negative power source potential to the logic gate formed in said circuit element region; said second cell contains a first internal wiring region containing a first cell connection wiring arranged in said first direction and having two ends, said two ends of said first cell connection wiring being respectively coupled to separate wirings formed in one of two of said adjacent wiring regions, said at least one standard cell row including said second cell being located between said two wiring regions, said first internal wiring region being situated between said positive power source line region and said circuit element region; and said second cell contains a second internal wiring region containing a second cell connection wiring arranged in said first direction and having two ends, said two ends of said second cell connection wiring being respectively coupled to separate wirings formed in the other of said two wiring regions, said second internal wiring region being situated between said negative power source line region and said circuitu element region.

Claim 7

The semiconductor integrated circuit device of claim 4 wherein at least one said standard cell row further contains at least one third standard cell containing a positive power source line region in which a positive power source line is formed; said third standard cell contains a negative power source line region in which a negative power source line is formed; and said third standard cell contains an internal wiring region, wherein cell connection wirings are arranged in the first direction, and which is situated between said positive power source line region and said negative power source line region.