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JPS6399545A Expired / Lapsed JP ⏱️ 0.0 years remaining

Integrated circuit using building block system

Assignee: Toshiba Corp
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Filing: 1987-09-28
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Granted: —
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Expires: 2007-09-28
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Abstract

Abstract PURPOSE:To reduce the area of a chip, by performing connection between separated logic block lines by way of wiring patterns, through which the logic blocks penetrate, in the logic block lines, which are present between said separated block lines. CONSTITUTION:An integrated circuit is formed so that gate wirings (a), (b) and (c) penetrate in the longitudinal direction of blocks. Connection can be performed either from the upper end side or the lower end side. A plurality of various kinds of penetrated blocks 17, 17... having such a constitution are aligned in the lateral direction. Lines 18, 18... are arranged so that they are separated to each other. Then wiring between the blocks is performed. When such a wiring is automatically formed with an electronic computer, the wiring between the penetrated wiring patterns of logic circuit blocks (a) and other logic circuit blocks is performed so that the end parts of the closer penetrated wiring patterns are connected. Thus the length of the wiring becomes short and the number of wiring pieces is decreased. In this way, the integrated circuit using a building block system, in which the area of a semiconductor chip can be reduced, is obtained.

Inventors

  • 👤 Yoshihisa Shioashi
  • 👤 塩足 慶久
  • 👤 Akihiro Sueda
  • 👤 末田 昭洋
  • 👤 Kazuyuki Uchida
  • 👤 内田 和幸

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 18:16
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/10

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS50154079A Cited

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