US5062079A
Expired / Lapsed
US
⏱️ 0.0 years remaining
MOS type random access memory with interference noise eliminator
Assignee: Toshiba Corp
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Filing: 1989-09-26
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Granted: 1991-10-29
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Expires: 2009-09-26
Abstract
Abstract A MOS type random access memory disclosed has a plurality of pairs of sequentially aligned folded type bit lines each of which has a first bit line and a second bit line. Memory cells are arranged at points of intersection between a memory cell word line and the first bit lines. Dummy cells are arranged at points of intersection of a dummy cell word line and the second bit lines. Sense amplifier circuits are connected to the bit line pairs, respectively. In a data read mode of the memory, when a bit data is read from a certain memory cell which is connected to a first word line selected and a first bit line of a selected bit line pair, a second bit line onto which a data voltage is read from a dummy cell of the selected bit line pair is forcedly fixed to a precharge voltage produced by a precharge voltage generator in a presented time interval after the first word line is selected and before a certain sense amplifier circuit connected to the selected bit line pair gets activated, whereby interference noise may be eliminated which is introduced onto the selected bit line pair from a bit line pair adjacent to the selected bit line pair.
Inventors
- 👤 Kenji Tsuchida
- 👤 Yukihito Oowaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:35
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4097; G11C11/4091
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
242 words
A dynamic random access memory comprising: (a) a plurality of pairs of folded bit lines sequentially aligned and respectively including first bit lines and second bit lines which form bit line pairs; (b) first and second word lines insulatively intersecting said plurality of pairs of folded bit lines at intersecting points therebetween; (c) memory cells arranged at the intersecting points between said first bit lines of the bit line pairs and said first word lines; (d) dummy cells arranged at the intersecting points between said second bit lines of the bit line pairs and said second word lines; (e) sense amplifier sections connected to said plurality of pairs of folded bit lines; and (f) voltage controller means for, when a selected memory cell which is connected to a selected word line and a first bit line of a selected bit line pair is subjected to data reading, causing a second bit line of said selected bit line pair to be in a low-impedance state in a predetermined time interval after said selected word line is designated and before a sense amplifier section connected to said selected bit line pair is activated, thereby eliminating interference noise applied to said selected bit line pair from a bit line pair adjacent to said selected bit line pair, said voltage controller means comprising switching means provided at said dummy cells for selectively connecting each second bit line of the bit line pairs to a constant voltage.
Claim 2
Dependent Claim
242 words
A dynamic random access memory comprising: (a) a plurality of pairs of folded bit lines sequentially aligned and respectively including first bit lines and second bit lines which form bit line pairs; (b) first and second word lines insulatively intersecting said plurality of pairs of folded bit lines at intersecting points therebetween; (c) memory cells arranged at the intersecting points between said first bit lines of the bit line pairs and said first word lines; (d) dummy cells arranged at the intersecting points between said second bit lines of the bit line pairs and said second word lines; (e) sense amplifier sections connected to said plurality of pairs of folded bit lines; and (f) voltage controller means for, when a selected memory cell which is connected to a selected word line and a first bit line of a selected bit line pair is subjected to data reading, causing a second bit line of said selected bit line pair to be in a low-impedance state in a predetermined time interval after said selected word line is designated and before a sense amplifier section connected to said selected bit line pair is activated, thereby eliminating interference noise applied to said selected bit line pair from a bit line pair adjacent to said selected bit line pair, said voltage controller means comprising switching means provided at said dummy cells for selectively connecting each second bit line of the bit line pairs to a constant voltage.
Claim 3
Dependent Claim
191 words
A dynamic random access memory comprising: (a) a plurality of pairs of bit lines sequentially aligned and respectively including first bit lines and second bit lines which form bit line pairs; (b) first and second word lines insulatively intersecting said plurality of pairs of bit lines to provide crossing points therebetween; (c) memory cells arranged at crossing points between said first bit lines and said first word lines; (d) dummy cells arranged at crossing points between said second bit lines and said second word lines; (e) sense amplifier sections connected respectively to said plurality of pairs of bit lines; and (f) voltage controller means for, when a selected memory cell which is connected to a selected word line and a first bit line of a selected bit line pair is subjected to data reading, causing neighboring bit lines, adjacent to the first bit line of the selected bit line pair at both sides thereof to be in an electrically separated condition or to be maintain at a preselected voltage potential, thereby eliminating interference noise applied from said neighboring bit lines to said first bit line of the selected bit line pair.
Claim 4
Dependent Claim
191 words
A dynamic random access memory comprising: (a) a plurality of pairs of bit lines sequentially aligned and respectively including first bit lines and second bit lines which form bit line pairs; (b) first and second word lines insulatively intersecting said plurality of pairs of bit lines to provide crossing points therebetween; (c) memory cells arranged at crossing points between said first bit lines and said first word lines; (d) dummy cells arranged at crossing points between said second bit lines and said second word lines; (e) sense amplifier sections connected respectively to said plurality of pairs of bit lines; and (f) voltage controller means for, when a selected memory cell which is connected to a selected word line and a first bit line of a selected bit line pair is subjected to data reading, causing neighboring bit lines, adjacent to the first bit line of the selected bit line pair at both sides thereof to be in an electrically separated condition or to be maintain at a preselected voltage potential, thereby eliminating interference noise applied from said neighboring bit lines to said first bit line of the selected bit line pair.
Claim 5
Dependent Claim
21 words
The memory according to claim 2, wherein said voltage controller means inactivates sense amplifier sections connected to said neighboring bit lines.
Claim 6
Dependent Claim
23 words
The memory according to claim 3, wherein said voltage controller means causes said neighboring bit lines to be fixed to a precharge voltage.
Claim 7
Dependent Claim
34 words
The memory according to claim 4, wherein said voltage controller means comprises: switching transistor means for disconnecting said selected bit line pair from the precharge voltage before said selected first word line is designated.
Claim 8
Dependent Claim
48 words
The memory according to claim 4, wherein said voltage controller means comprises: switching transistor means for disconnecting all of the first and second bit lines including said selected bit line pair and said neighboring bit lines from the precharge voltage before said selected first word line is designated.
Claim 9
Dependent Claim
22 words
The memory according to claim 1, wherein said switching means comprises a voltage-controlled switching transistor arranged at one of said dummy cells.
Claim 10
Dependent Claim
28 words
The memory according to claim 1, wherein said switching means comprises voltage-controlled switching transistors arranged in dummy cells which are associated with one of said second word lines.
Claim 11
Dependent Claim
50 words
The memory according to claim 8, wherein said switching transistors comprises field effect transistor having drains which are connected in common to a constant voltage and gates connected together by a wiring line, said field effect transistors being rendered conductive in response to a voltage potential on said wiring line.
Claim 12
Dependent Claim
31 words
The memory according to claim 9, wherein each of said field effect transistors has a source thereof connected to a dummy cell transistor of a corresponding one of said dummy cells.
References Cited (Backward Citations)
US4379344A
Cited
GB2114811A
Cited
US4667311A
Cited
JPS6342095A
Cited
EP0264929A2
Cited
JPS63104296A
Cited
JPH01130392A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-28 | 1995-04-29 | 1995-10-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-28 | 1999-04-29 | 1999-10-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-28 | 2003-04-29 | 2003-10-29 | $7700.00 | Window Closed / Lapsed |