Patent US5060066A successfully refreshed from Google Patents.
US5060066A
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US
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Integrating-phase lock method and circuit for synchronizing overlay displays on cathode-ray-tube monitors of digital graphic information and video image information and the like
Assignee: 3M Innovative Properties Co
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Filing: 1989-02-21
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Granted: 1991-10-22
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Expires: 2009-02-21
Abstract
Abstract A novel separate synchronizing error signal integrating filter section and error signal phase lock loop section independently controllable for such purposes as controlling the horizontal synchronization of overlayed video and graphic display rasters, particularly during periods of aberrant operation.
Inventors
- 👤 Jerry B. Roberts
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 14:43
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/04; H04N5/12; H04N5/126
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
129 words
A method of horizontal sychronizing of overlayed digital graphic image information and video image information in the same display area of a cathode-ray-tube monitor screen, that comprises, applying phase error voltage signals along a pair of independently operative paths, one integrating the phase error voltage to obtain zero tracking error and the other serving phase loop locking functions; summing the output of both paths for control of the clocking of the graphic image information; and controlling the separate operation of the paths in accordance with display signal aberrations, maintaining the phase lock loop operative in response to the phase error signals during the aberrations while disconnecting the integrating path from such phase error signals during such aberrations, and varying the time constants of one or both of said paths.
Claim 2
Independent Claim
129 words
A method of horizontal sychronizing of overlayed digital graphic image information and video image information in the same display area of a cathode-ray-tube monitor screen, that comprises, applying phase error voltage signals along a pair of independently operative paths, one integrating the phase error voltage to obtain zero tracking error and the other serving phase loop locking functions; summing the output of both paths for control of the clocking of the graphic image information; and controlling the separate operation of the paths in accordance with display signal aberrations, maintaining the phase lock loop operative in response to the phase error signals during the aberrations while disconnecting the integrating path from such phase error signals during such aberrations, and varying the time constants of one or both of said paths.
Claim 3
Dependent Claim
30 words
A method as claimed in claim 1 and in which said aberrations occur during the equalization pulses of the vertical frame and when no video information is to be displayed.
Claim 4
Dependent Claim
42 words
A method as claimed in claim 2 and in which said graphic image information is applied as a still frame overlaying the video display and said disconnecting and reconnecting of the integrating path obviates flutter at the top of the overlayed display.
Claim 5
Dependent Claim
128 words
In an integrating-phase lock loop circuit for horizontal synchronizing of overlayed digital graphic image information and video image information in the display area of a cathode-ray-tube monitor, a pair of independently operative filter sections, one provided with network means for integrating phase error voltage signals to obtain zero tracking error and the other provided with network means for phase loop locking functions; switching means for selectively and independently connecting each of the filter sections to and disconnecting the same from a source of phase error voltage representing horizontal synchronizing phase errors between the video and graphic image information; means for summing the outputs of the filter sections; and means for applying the sum outputs to voltage controlled oscillator means for controlling the clocking of the graphic image information.
Claim 6
Dependent Claim
128 words
In an integrating-phase lock loop circuit for horizontal synchronizing of overlayed digital graphic image information and video image information in the display area of a cathode-ray-tube monitor, a pair of independently operative filter sections, one provided with network means for integrating phase error voltage signals to obtain zero tracking error and the other provided with network means for phase loop locking functions; switching means for selectively and independently connecting each of the filter sections to and disconnecting the same from a source of phase error voltage representing horizontal synchronizing phase errors between the video and graphic image information; means for summing the outputs of the filter sections; and means for applying the sum outputs to voltage controlled oscillator means for controlling the clocking of the graphic image information.
Claim 7
Dependent Claim
25 words
An integrating-phase lock loop circuit as claimed in claim 4 and in which said switching means are controlled in accordance with desired graphic display information.
Claim 8
Dependent Claim
65 words
An integrating-phase lock loop circuit as claimed in claim 4 and in which means is provided forcontrolling the said switching means to maintain the phase lock loop filter section operative in response to phase error signals during such periods as display signal aberrations, and circuit and vertical scan interval aberrations, to effect phase locking while disconnecting the integrating filter section from said phase error signals.
Claim 9
Dependent Claim
34 words
An integrating-phase lock loop circuit as claimed in claim 4 and in which means is provided for varying the time constant of the phase lock loop section to enable faster operation during such aberrations.
Claim 10
Dependent Claim
30 words
An integrating-phase lock loop circuit as claimed in claim 4 and in which means is provided for selectively varying the time constants of one or both of said filter sections.
Claim 11
Dependent Claim
120 words
An integrating-phase lock loop circuit as claimed in claim 4 and in which the integrating network means normally operates in a proportional mode until said phase error or a frequency error exceeds predetermined minimum values, whereupon means is provided for switching in current source means to cause the integrating network means to slew towards the point of zero tracking error while lock is re-acquired during the continued operation of the phase loop locking network means and with the first subsequent reversal in direction of phase error providing an indication that such zero tracking point has been reached; and means further being provided for thereupon terminating the slewing and restoring the integrating network to operation in said proportional mode of operation.
Claim 12
Independent Claim
199 words
A method of horizontal sychronizing of overlayed digital graphic image information and video image information in the same display area of a cathode-ray-tube monitor screen, that comprises, applying phase error voltage signals along a pair of independently operative paths, one integrating the phase error voltage to obtain zero tracking error and the other serving phase loop locking functions; summing the output of both paths for control of the clocking of the graphic image information; and controlling the separate operation of the paths in accordance with display signal aberrations, maintaining the phase lock loop operative in response to the phase error signals during the aberrations while disconnecting the integrating path from such phase error signals during such aberrations, and in which the integrating normally operates in a proportional mode until said phase error or a frequency error exceeds predetermined minimum values, whereupon the integrating commences slewing towards the point of zero tracking error while lock is re-acquired during continued operation of the phase loop locking, with the first subsequent reversal in direction of phase error providing an indication that such zero tracking point has been reached, whereupon the slewing terminates and the integrating returns to said proportional mode of operation.
Claim 13
Independent Claim
199 words
A method of horizontal sychronizing of overlayed digital graphic image information and video image information in the same display area of a cathode-ray-tube monitor screen, that comprises, applying phase error voltage signals along a pair of independently operative paths, one integrating the phase error voltage to obtain zero tracking error and the other serving phase loop locking functions; summing the output of both paths for control of the clocking of the graphic image information; and controlling the separate operation of the paths in accordance with display signal aberrations, maintaining the phase lock loop operative in response to the phase error signals during the aberrations while disconnecting the integrating path from such phase error signals during such aberrations, and in which the integrating normally operates in a proportional mode until said phase error or a frequency error exceeds predetermined minimum values, whereupon the integrating commences slewing towards the point of zero tracking error while lock is re-acquired during continued operation of the phase loop locking, with the first subsequent reversal in direction of phase error providing an indication that such zero tracking point has been reached, whereupon the slewing terminates and the integrating returns to said proportional mode of operation.
References Cited (Backward Citations)
US4093963A
Cited
JPS61224571A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-21 | 1995-04-22 | 1995-10-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-21 | 1999-04-22 | 1999-10-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-21 | 2003-04-22 | 2003-10-22 | $7700.00 | Window Closed / Lapsed |