Computer gate control circuitry and apparatus to enable a single computer to simultaneously and selectively control a multiplicity of hard disk drives

Claim 2

A gate control circuitry and apparatus for using a single computer to control a multiplicity of hard disk drives simultaneously and selectively, the single computer having a multiplicity of control lines, a multiplicity of data lines, and a multiplicity of input/output address lines including a hard disk drive address line and a primary and secondary hard disk drive addresses switching line, the gate control circuitry and apparatus comprising: a. a latch means connected to said single computer by said multiplicity of data lines; b. a multiplicity of gate means each connected to said latch means and corresponding to a respective one of said multiplicity of data lines; c. a multiplicity of hard disk dive controller means each connected to a respective one of said multiplicity of gate means; d. each of said multiplicity of control lines and said multiplicity of input/output address lines, except said hard disk drive address line and said primary and secondary hard disk drive addresses switching line, connected to a decoder means and then branched off into each of said multiplicity of hard disk drive controller means; e. said hard disk drive address line connected to said decoder means and then branched off into each of said multiplicity of gate means; f. said primary and secondary hard disk drive addresses switching line connected to an invertor means and then branched off into each of said multiplicity of hard disk drive controller means; and g. said latch means also connected to said decoder means; h. whereby said decoder means can decode a latch control signal received from said single computer and send a decoded latch control signal to said latch means, which in turn will control said multiplicity of gate means to be opened or closed individually for said hard disk drive address line, so that said multiplicity of hard disk drive controller means can be activated or deactivated individually, to thereby enable said single computer to control said multiplicity of hard disk drives simultaneously and selectively for operations such as preparation, diagnosis or data storage.

Claim 3

A gate control circuitry and apparatus in accordance with claim 1 further comprising: a. an additional latch means connected to said single computer by said multiplicity of data lines; b. a system gate means connected to said additional latch means; c. a system hard disk drive controller means connected to said system gate means; d. each of said multiplicity of control lines and said multiplicity of input/output address lines also connected to said system hard disk drive controller means but not connected to said hard disk drive address line; e. said hard disk drive address line also connected to said system gate means; f. a three-way electronic switch means connected to said primary and secondary hard disk drive addresses switching line and said invertor means, and controlled by said additional latch means such that the three-way electronic switch means can be switched to let said primary and secondary hard disk drive addresses switching line go through or bypass said invertor means; and g. said additional latch means also connected to said decoder means; h. whereby said decoder means can decode an additional latch control signal received from said single computer and send an additional decoded latch control signal to said additional latch means, which in turn will switch said three-way electronic switch means to let said primary and secondary hard disk drive addresses switching line bypass said invertor means and close said system gate means for said hard disk drive address line to disable said system hard disk drive controller means, to thereby enable said single computer to control said multiplicity of hard disk drives simultaneously and selectively as primary hard disk drives for operations such as preparation, diagnosis or data storage.

Claim 4

A gate control circuitry and apparatus for using a single computer to control a multiplicity of hard disk drives simultaneously and selectively, the single computer having a multiplicity of control lines, sixteen data lines, and twenty input/output address lines including a hard disk drive address line and a primary and secondary hard disk drive addresses switching line, the gate control circuitry and apparatus comprising: a. a latch means connected to said single computer by said sixteen data lines; b. a multiplicity of gate means each connected to said latch means and corresponding to a respective one of said sixteen data lines; c. a multiplicity of hard disk drive controller means each connected to a respective one of said multiplicity of gate means; d. each of said multiplicity of control lines and said twenty input/output address lines, except said hard disk drive address line and said primary and secondary hard disk drive addresses switching line, connected to a decoder means and then branched off into each of said multiplicity of hard disk drive controller means; e. said hard disk drive address line connected to said decoder means and then branched off into each of said multiplicity of gate means; f. said primary and secondary hard disk drive addresses switching line connected to an invertor means and then branched off into each of said multiplicity of hard disk drive controller means; and g. said latch means also connected to said decoder means; h. whereby said decoder means can decode a latch control signal received from said single computer and send a decoded latch control signal to said latch means, which in turn will control said multiplicity of gate means to be opened or closed individually for said hard disk drive address line, so that said multiplicity of hard disk drive controller means can be activated or deactivated individually, to thereby enable said single computer to control said multiplicity of hard disk drives simultaneously and selectively for operations such as preparation, diagnosis or data storage.

Claim 5

A gate control circuitry and apparatus for using a single computer to control a multiplicity of hard disk drives simultaneously and selectively, the single computer having a multiplicity of control lines, sixteen data lines, and twenty input/output address lines including a hard disk drive address line and a primary and secondary hard disk drive addresses switching line, the gate control circuitry and apparatus comprising: a. a latch means connected to said single computer by said sixteen data lines; b. a multiplicity of gate means each connected to said latch means and corresponding to a respective one of said sixteen data lines; c. a multiplicity of hard disk drive controller means each connected to a respective one of said multiplicity of gate means; d. each of said multiplicity of control lines and said twenty input/output address lines, except said hard disk drive address line and said primary and secondary hard disk drive addresses switching line, connected to a decoder means and then branched off into each of said multiplicity of hard disk drive controller means; e. said hard disk drive address line connected to said decoder means and then branched off into each of said multiplicity of gate means; f. said primary and secondary hard disk drive addresses switching line connected to an invertor means and then branched off into each of said multiplicity of hard disk drive controller means; and g. said latch means also connected to said decoder means; h. whereby said decoder means can decode a latch control signal received from said single computer and send a decoded latch control signal to said latch means, which in turn will control said multiplicity of gate means to be opened or closed individually for said hard disk drive address line, so that said multiplicity of hard disk drive controller means can be activated or deactivated individually, to thereby enable said single computer to control said multiplicity of hard disk drives simultaneously and selectively for operations such as preparation, diagnosis or data storage.

Claim 6

A gate control circuitry and apparatus in accordance with claim 3 further comprising: a. an additional latch means connected to said single computer by said sixteen data lines; b. a system gate means connected to said additional latch means; c. a system hard disk drive controller means connected to said system gate means; d. each of said multiplicity of control lines and said twenty input/output address lines, except said hard disk drive address line, also connected to said system hard disk drive controller means; e. said hard disk drive address line also connected to said system gate means; f. a three-way electronic switch means connected to said primary and secondary hard disk drive addresses switching lines and said invertor means, and controlled by said additional latch means such that the three-way electronic switch means can be switched to let said primary and secondary hard disk drive addresses switching line go through or bypass said invertor means; and g. said additional latch means also connected to said decoder means; h. whereby said decoder means can decode an additional latch control signal received from said single computer and send an additional decoded latch control signal to said additional latch means, which in turn will switch said three-way electronic switch means to let said primary and secondary hard disk drive addresses switching line bypass said invertor means, and close said system gate means for said hard disk drive address line to disable said system hard disk drive controller means, to thereby enable said single computer to control said multiplicity of hard disk drives simultaneously and selectively as primary hard disk drives for operations such as preparation, diagnosis or data storage.

Claim 7

A gate control circuitry and apparatus for using a single computer to control a multiplicity of hard disk drives simultaneously and selectively, the single computer having a multiplicity of control lines, a multiplicity of data lines, and a multiplicity of input/output address lines including a hard disk drive address line and a primary and secondary hard disk drive addresses switching line, the gate control circuitry and apparatus comprising: a. a multiplicity of latch means; b. each of said multiplicity of data lines branched off into a respective one of said multiplicity of latch means; c. a multiplicity of gate means each connected to said multiplicity of latch means and corresponding to a respective one of said multiplicity of data lines; d. a multiplicity of hard disk drive controller means each connected to a respective one of said multiplicity of gate means; e. each of said multiplicity of control lines and said multiplicity of input/output address lines, except said hard disk drive address lien and said primary and secondary hard disk drive address switching line, connected to a decoder means and then branched off into each of said multiplicity of hard disk drive controller means; f. said hard disk drive address line connected to said decoder means and then branched off into each of said multiplicity of gate means; g. said primary and secondary hard disk drive addresses switching line connected to an invertor means and then branched off into each of said multiplicity of hard disk drive controller means; and h. said multiplicity of latch means also connected to said decoder means; i. whereby said decoder means can decode a latch control signal received from said single computer and send a decoded latch control signal to said multiplicity of latch means, which in turn will control said multiplicity of gate means to be opened or closed individually for said hard disk drive address line, so that said multiplicity of hard disk drive controller means can be activated or deactivated individually, to thereby enable said single computer to control said multiplicity of hard disk drives simultaneously and selectively for operations such as preparation, diagnosis or data storage.

Claim 8

A gate control circuitry and apparatus for using a single computer to control a multiplicity of hard disk drives simultaneously and selectively, the single computer having a multiplicity of control lines, a multiplicity of data lines, and a multiplicity of input/output address lines including a hard disk drive address line and a primary and secondary hard disk drive addresses switching line, the gate control circuitry and apparatus comprising: a. a multiplicity of latch means; b. each of said multiplicity of data lines branched off into a respective one of said multiplicity of latch means; c. a multiplicity of gate means each connected to said multiplicity of latch means and corresponding to a respective one of said multiplicity of data lines; d. a multiplicity of hard disk drive controller means each connected to a respective one of said multiplicity of gate means; e. each of said multiplicity of control lines and said multiplicity of input/output address lines, except said hard disk drive address lien and said primary and secondary hard disk drive address switching line, connected to a decoder means and then branched off into each of said multiplicity of hard disk drive controller means; f. said hard disk drive address line connected to said decoder means and then branched off into each of said multiplicity of gate means; g. said primary and secondary hard disk drive addresses switching line connected to an invertor means and then branched off into each of said multiplicity of hard disk drive controller means; and h. said multiplicity of latch means also connected to said decoder means; i. whereby said decoder means can decode a latch control signal received from said single computer and send a decoded latch control signal to said multiplicity of latch means, which in turn will control said multiplicity of gate means to be opened or closed individually for said hard disk drive address line, so that said multiplicity of hard disk drive controller means can be activated or deactivated individually, to thereby enable said single computer to control said multiplicity of hard disk drives simultaneously and selectively for operations such as preparation, diagnosis or data storage.

Claim 9

A gate control circuitry and apparatus in accordance with claim 5 further comprising: a. an additional latch means connected to said single computer by said multiplicity of data lines; b. a system gate means connected to said additional latch means; c. a system hard disk drive controller means connected to said system gate means; d. each of said multiplicity of control lines and said multiplicity of input/output address lines, except said hard disk drive address line, also connected to said system hard disk drive controller means; e. said hard disk drive address line also connected to said system gate means; f. a three-way electronic switch means connected to said primary and secondary hard disk drive addresses switching line and said invertor means, and controlled by said additional latch means such that the three-way electronic switch means can be switched to let said primary and secondary hard disk drive addresses switching line to go through or bypass said invertor means; and g. said additional latch means also connected to said decoder means; h. whereby said decoder means can decode an additional latch control signal received from said single computer and send an additional decoded latch control signal to said additional latch means, which in turn will switch said three-way electronic switch means to let said primary and secondary hard disk drive addresses switching line bypass said invertor means, and close said system gate means for said hard disk drive address line to disable said system hard disk drive controller means, to thereby enable said single computer to control said multiplicity of hard disk drives simultaneously and selectively as primary hard disk drives for operations such as preparation, diagnosis or data storage.

Claim 10

A gate control circuitry and apparatus for using a single computer to control a multiplicity of computer component devices simultaneously and selectively, the single computer having a multiplicity of control lines, a multiplicity of data lines, and a multiplicity of input/output address lines including a computer component device address line and a primary and secondary computer component device address switching line, the gate control circuitry and apparatus comprising: a. a multiplicity of latch means; b. each of said multiplicity of data lines branched off into a respective one of said multiplicity of latch means; c. a multiplicity of gate means each connected to said multiplicity of latch means and corresponding to a respective one of said multiplicity of data lines; d. a multiplicity of computer component device controller means each connected to a respective one of said multiplicity of gate means; e. each of said multiplicity of control lines and said multiplicity of input/output address lines, except said computer component device address line and said primary and secondary computer component device addresses switching line, connected to a decoder means and then branched off into each of said multiplicity of computer component device controller means; f. said computer component device address line connected to said decoder means and then branched off into each of said multiplicity of gate means; g. said primary and secondary computer component device address switching line connected to an invertor means an then branched off into each of said multiplicity of computer component device controller means; and h. said multiplicity of latch means also connected to said decoder means; i. whereby said decoder means can decode a latch control signal received from said single computer and send a decoded latch control signal to said multiplicity of latch means, which in turn will control said multiplicity of gate means to be opened or closed individually for said computer component device address line, so that said multiplicity of computer component device controller means can be activated or deactivated individually, to thereby enable said single computer to control said multiplicity of computer component devices simultaneously and selectively for operations such as preparation, diagnosis or data storage.

Claim 11

A gate control circuitry and apparatus for using a single computer to control a multiplicity of computer component devices simultaneously and selectively, the single computer having a multiplicity of control lines, a multiplicity of data lines, and a multiplicity of input/output address lines including a computer component device address line and a primary and secondary computer component device address switching line, the gate control circuitry and apparatus comprising: a. a multiplicity of latch means; b. each of said multiplicity of data lines branched off into a respective one of said multiplicity of latch means; c. a multiplicity of gate means each connected to said multiplicity of latch means and corresponding to a respective one of said multiplicity of data lines; d. a multiplicity of computer component device controller means each connected to a respective one of said multiplicity of gate means; e. each of said multiplicity of control lines and said multiplicity of input/output address lines, except said computer component device address line and said primary and secondary computer component device addresses switching line, connected to a decoder means and then branched off into each of said multiplicity of computer component device controller means; f. said computer component device address line connected to said decoder means and then branched off into each of said multiplicity of gate means; g. said primary and secondary computer component device address switching line connected to an invertor means an then branched off into each of said multiplicity of computer component device controller means; and h. said multiplicity of latch means also connected to said decoder means; i. whereby said decoder means can decode a latch control signal received from said single computer and send a decoded latch control signal to said multiplicity of latch means, which in turn will control said multiplicity of gate means to be opened or closed individually for said computer component device address line, so that said multiplicity of computer component device controller means can be activated or deactivated individually, to thereby enable said single computer to control said multiplicity of computer component devices simultaneously and selectively for operations such as preparation, diagnosis or data storage.

Claim 12

A gate control circuitry and apparatus in accordance with claim 7 wherein said multiplicity of computer component devices are computer tape drives.

Claim 13

A gate control circuitry and apparatus in accordance with claim 7 wherein said multiplicity of computer component devices are computer floppy diskette drives.

Claim 14

A gate control circuitry and apparatus in accordance with claim 7 further comprising: a. an additional latch means connected to said single computer by said multiplicity of data lines; b. a system gate means connected to said additional latch means; c. a system computer component device controller means connected to said system gate means; d. each of said multiplicity of control lines and said multiplicity of input/output address lines, except said computer component device address line, also connected to said system computer component device controller means; e. said computer component device address line also connected to said system gate means; f. a three-way electronic switch means connected to said primary and secondary computer component device address switching line and said invertor means, and controlled by said additional latch means such that the three-way electronic switch means can be switched to let said primary and secondary computer component device addresses switching line to go through or bypass said invertor means; and g. said additional latch means also connected to said decoder means; h. whereby said decoder means can decode an additional latch control signal received from said single computer and send an additional decoded latch control signal to said additional latch means, which in turn will switch said three-way electronic switch means to let said primary and secondary computer component device addresses switching line bypass said invertor means, and close said system gate means for said computer component device address line to disable said system computer component device controller means, to thereby enable said single computer to control said multiplicity of computer component devices simultaneously and selectively as primary computer component devices for operations such as preparation, diagnosis or data storage.

Claim 15

A gate control circuitry and apparatus in accordance with claim 10 wherein said multiplicity of computer component devices are computer tape drives.

Claim 16

A gate control circuitry and apparatus in accordance with claim 10 wherein said multiplicity of computer component devices are computer floppy diskette drives.