US4937783A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Peripheral controller for executing multiple event-count instructions and nonevent-count instructions in a prescribed parallel sequence
Assignee: Advanced Micro Devices Inc
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Filing: 1987-08-17
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Granted: 1990-06-26
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Expires: 2007-08-17
Abstract
Abstract A typical peripheral system includes a control path and a data path along with a peripheral controller that processes different type of instructions for control and data paths. Since control and data paths are not independent of each other, it is necessary to either combine these two types of instructions in a single instruction or execute these two types of instructions in a prescribed manner so that a control path instruction can be executed while a data path instruction is being executed. The data path instructions (which may also be called event-count instructions) includes serialization and deserialization of data and other information such as ECC, and typically have lengths of events, or fields, typically in words and bytes associated with them. Control instructions (which may also be referred to as nonevent-count instructions) include setting of tag patterns, branching or jumping or typically have no fields of data associated with them. In the present invention, the peripheral controller can execute nonevent-count instructions before the end of a previous event-count instruction, and when a next event-count instruction is fetched, it must wait for the end of a previous event-count instruction before the new event-count instruction can be executed. In this way, all nonevent-count instructions between two event-count instructions, for both contiguous and noncontiguous event-count instructions, can be executed in sequence, and the timing dependencies between these two different types of instructions can be maintained.
Inventors
- 👤 Sai-Keung Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:51
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/10; G06F13/12; G06F13/124; G06F13/126
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
241 words
A single processing unit for communicating with a peripheral device and for providing instructions to said peripheral device, said single processing unit including a peripheral controller having an input for receiving parallel bit instruction signals from a computer and for processing multiple instruction signals from said computer, wherein said peripheral controller includes a sequencer comprising: an instruction memory for storing peripheral controller instruction signals formed of parallel bits, said instruction memory having an input for receiving address signals and an output for providing peripheral controller instruction signals; an address generator for generating address signals for selecting peripheral controller instruction signals stored in said instruction memory, said address generator having an input for receiving control signals and an output for providing address signals; means coupling the output of said address generator to the input of said instruction memory; an address controller having input circuit for receiving address control signals and an output for providing control signals to said address generator; means coupling the output of said address controller to the input of said address generator; an instruction decoder including means for separating peripheral controller instructions signals into event-count instruction and nonevent-count instructions, said instruction decoder having an input for receiving peripheral controller instruction signals from said instruction memory, and a first output for providing even-count instruction signals and a second output for providing nonevent-count instruction signals; and means coupling the output of said instruction memory to said input of said instruction decoder.
Claim 2
Dependent Claim
241 words
A single processing unit for communicating with a peripheral device and for providing instructions to said peripheral device, said single processing unit including a peripheral controller having an input for receiving parallel bit instruction signals from a computer and for processing multiple instruction signals from said computer, wherein said peripheral controller includes a sequencer comprising: an instruction memory for storing peripheral controller instruction signals formed of parallel bits, said instruction memory having an input for receiving address signals and an output for providing peripheral controller instruction signals; an address generator for generating address signals for selecting peripheral controller instruction signals stored in said instruction memory, said address generator having an input for receiving control signals and an output for providing address signals; means coupling the output of said address generator to the input of said instruction memory; an address controller having input circuit for receiving address control signals and an output for providing control signals to said address generator; means coupling the output of said address controller to the input of said address generator; an instruction decoder including means for separating peripheral controller instructions signals into event-count instruction and nonevent-count instructions, said instruction decoder having an input for receiving peripheral controller instruction signals from said instruction memory, and a first output for providing even-count instruction signals and a second output for providing nonevent-count instruction signals; and means coupling the output of said instruction memory to said input of said instruction decoder.
Claim 3
Dependent Claim
36 words
A single processing unit as in claim 1, wherein each of said instruction signals from said instruction memory are composed of multiple bits that are fed in parallel from said instruction memory to said instruction decoder.
Claim 4
Dependent Claim
41 words
A single processing unit as in claim 2, wherein one of the bits or a combination of a predetermined pattern of bits of said instruction signals received after a pause determines whether said first instruction is an event-count or nonevent-count instruction.
Claim 5
Dependent Claim
36 words
A single processing unit as in claim 1, wherein said instruction decoder comprises a first logic circuit for generating nonevent-count instructions and a second logic circuit for generating event-count instructions in response to said instruction signals.
Claim 6
Dependent Claim
61 words
A single processing unit as in claim 4, wherein said first logic circuit comprises a first group of AND gates having first and second inputs, first inputs of said AND gates being connected in parallel and coupled to receive a PAUSE signal, and the second input of said AND gates being connected to receive an instruction signal from said instruction memory.
Claim 7
Dependent Claim
103 words
A single processing unit as in claim 4, wherein said second logic circuit comprises a plurality of multiplexors including a number of D-type flip-flops, each of said D-type flip-flops having a D-input; a second group of AND gates having inputs coupled respectively to the output of said flip-flops; a third group of AND gates whose inputs coupled to said instruction memory for receiving instruction signals; and a group of logic OR gate inputs respectively coupled to the outputs of said second and third groups of AND gates, wherein the D-inputs of said flip-flops are coupled to the outputs of said logic OR gates.
Claim 8
Dependent Claim
20 words
A single processing unit as in claim 6, including means for applying a clock signal to each of said flip-flops.
Claim 9
Dependent Claim
118 words
A single processing unit as in claim 1, wherein said peripheral controller comprises: a synchronizer and control circuit having a first input for receiving a RESET signal, and a first output coupled to the input of said sequencer, said synchronizer and control circuit including means responsive to the receipt of a RESET signal at said first input for generating a PAUSE signal at said first output of said synchronizer and control circuit; module means coupled to said first and second outputs of said instruction decoder included in said sequencer for processing said event-count and nonevent-count instructions; and an event-counter having an output coupled to said sequencer for providing a signal to said sequencer for fetching a new instruction.
Claim 10
Dependent Claim
106 words
A single processing unit as in claim 8, wherein said module means comprises: a first module having an input coupled to said second output of said instruction decoder, said first module including circuit means for decoding nonevent-count instructions; a second module having an input coupled to said first output of said instruction decoder, said second module including circuit means for decoding event-count instructions; and a third module having a first input coupled to said first output of said instruction decoder, and a second input coupled to said second output of said instruction decoder, said third module including circuit means for decoding both event-count and nonevent-count instructions.
Claim 11
Dependent Claim
43 words
A single processing unit as in claim 9, wherein said module means includes a fourth module having an input coupled to said first output of said synchronizer and control circuit, said fourth module including means for providing status control of said peripheral controller.
Claim 12
Dependent Claim
160 words
A single processing unit as in claim 8, wherein said event-counter comprises: a memory for storing a number representative of the number of cycles included in an event-count instruction, said memory providing said number at an output; a down counter having a first input coupled to said output of said memory means for receiving said number representative of the cycles in an event-count instruction and a second input coupled to said module means for receiving cycle counts produced by said module means, said down counter including means for counting down from said number and providing at an output of said down counter a signal indicating that said down counter has reached zero; a zero detect circuit having an input coupled to said output of said down counter for detecting when said signal at said output of said down counter indicates that said down counter has reached zero, thereby indicating that the system is ready to process a new instruction signal.
Claim 13
Dependent Claim
64 words
A single processing unit as in claim 11, wherein said event-counter further includes: a multiplexor coupled to the output of said zero detect circuit and to the input of said down counter; means for providing control signals from such second and third modules to said multiplexor; and a decoder for receiving an event-count instruction and for decoding said instruction for application to said multiplexor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-06-25 | 1993-12-25 | 1994-06-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-25 | 1997-12-25 | 1998-06-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-25 | 2001-12-25 | 2002-06-26 | $7700.00 | Window Closed / Lapsed |