Permeable base transistor with gate fingers

Claim 2

A permeable base transistor comprising: a semi-insulating semiconductor layer having a thickness; doped source and drain regions highly doped relative to said layer spaced from and opposite each other in said semi-insulating semiconductor layer; and a buried metal gate electrode including at least one current permeable aperture disposed between said source and drain regions within said layer so that a channel current flowing between said source and drain regions flows through the aperture and transverse to the thickness of said semi-insulating semiconductor layer wherein said buried metal gate electrode includes a plurality of buried metal gate electrode fingers disposed along a circle in said semi-insulating semiconductor layer with predetermined intervals therebetween, and one of said drain and source regions comprises a cylindrical region disposed inwardly from said buried metal gate electrode fingers and the other of said source and drain regions comprises an annular region disposed outwardly from and surrounding said buried metal gate electrode fingers.

Claim 3

A permeable base transistor as defined in claim 1 wherein said buried metal gate electrode includes said plurality of buried metal gate electrode fingers disposed along a circumference of several hundreds of microns with an interval of about 0.1 to 10 microns between adjacent gate electrode fingers and the gate length is less than 0.5 micron.

Claim 4

A permeable base transistor as defined in claim 1 including a gate contacting electrode electrically connected to said plurality of buried gate electrode fingers.

Claim 5

A permeable base transistor as defined in claim 3 wherein said gate contacting electrode is not in contact with said layer.

Claim 6

A permeable base transistor comprising: a semi-insulating semiconductor bulk crystal substrate having a thickness; source and drain regions highly doped relative to said bulk crystal substrate spaced from and opposite each other in said semi-insulating semiconductor bulk crystal substrate; a semiconductor gate having a gate length less than 0.5 micron and a low resistance relative to said bulk crystal substrate comprising a plurality of gate fingers disposed along a straight line several hundreds of microns in length with a predetermined interval of about 0.1 to 10 microns between adjacent gate fingers, said gate fingers being disposed within said bulk crystal substrate between said source and drain regions including at least one current permeable aperture so that a channel current flowing between said source and drain regions flows through the aperture and transverse to the thickness of said semi-insulating semiconductor bulk crystal substrate; and a gate contacting electrode electrically contacting said gate and spaced from said bulk crystal substrate.

Claim 7

A permeable base transistor comprising: a semi-insulating semiconductor bulk crystal substrate having a thickness; source and drain regions highly doped relative to said bulk crystal substrate spaced from and opposite each other in said semi-insulating semiconductor bulk crystal substrate; a semiconductor gate having a gate length less than 0.5 micron and a low resistance relative to said bulk crystal substrate comprising a plurality of gate fingers disposed along a straight line several hundreds of microns in length with a predetermined interval of about 0.1 to 10 microns between adjacent gate fingers, said gate fingers being disposed within said bulk crystal substrate between said source and drain regions including at least one current permeable aperture so that a channel current flowing between said source and drain regions flows through the aperture and transverse to the thickness of said semi-insulating semiconductor bulk crystal substrate; and a gate contacting electrode electrically contacting said gate and spaced from said bulk crystal substrate.

Claim 8

A permeable base transistor as defined in claim 5 wherein said semi-insulating semiconductor bulk crystal substrate is GaAs.

Claim 9

A permeable base transistor as defined in claim 5 wherein said semi-insulating semiconductor bulk crystal substrate is chosen from the group of semiconductors consisting of III-V semiconducting compounds and Si.

Claim 10

A permeable base transistor comprising: a semi-insulating semiconductor layer having a thickness; source and drain regions highly doped relative to said layer spaced from and opposite each other in said semi-insulating semiconductor layer; and a buried metal gate electrode including at least one current permeable aperture disposed between said source and drain regions within said layer so that a channel current flowing between said source and drain regions flows through the aperture and transverse to the thickness of said semi-insulating semiconductor layer wherein said buried metal gate electrode comprises a plurality of buried metal gate electrode fingers buried in said layer and disposed in a straight line with predetermined intervals therebetween along a length of several hundred microns with an interval of about 0.1 to 10 microns between adjacent buried metal gate electrode fingers and the gate length is less than 0.5 micron.

Claim 11

A permeable base transistor comprising: a semi-insulating semiconductor layer having a thickness; source and drain regions highly doped relative to said layer spaced from and opposite each other in said semi-insulating semiconductor layer; and a buried metal gate electrode including at least one current permeable aperture disposed between said source and drain regions within said layer so that a channel current flowing between said source and drain regions flows through the aperture and transverse to the thickness of said semi-insulating semiconductor layer wherein said buried metal gate electrode comprises a plurality of buried metal gate electrode fingers buried in said layer and disposed in a straight line with predetermined intervals therebetween along a length of several hundred microns with an interval of about 0.1 to 10 microns between adjacent buried metal gate electrode fingers and the gate length is less than 0.5 micron.

Claim 12

A permeable base transistor as defined in claim 8 including a gate contacting electrode electrically connected to said plurality of buried gate electrode fingers.

Claim 13

A permeable base transistor as defined in claim 9 wherein said gate contacting electrode is not in contact with said layer.

Claim 14

A permeable base transistor as defined in claim 8 wherein said semi-insulating semiconductor layer is a bulk crystal GaAs substrate.

Claim 15

A permeable base transistor as defined in claim 8 wherein said semi-insulating semiconductor layer is a bulk crystal substrate chosen from the group of semiconductors consisting of III-V semiconductor compounds and Si.

Claim 16

A permeable base transistor as defined in claim 8 wherein said semi-insulating semiconductor layer comprises an epitaxial layer having an impurity concentration of less than 10 14 cm -3 which is disposed on a semi-insulating GaAs substrate.

Claim 17

A permeable base transistor comprising: a semi-insulating semiconductor bulk crystal substrate having a thickness; source and drain regions highly doped relative to said bulk crystal substrate spaced from and opposite each other in said semi-insulating semiconductor bulk crystal substrate; a semiconductor gate having a low resistance relative to said bulk crystal substrate comprising a plurality of gate fingers disposed along a circle within said bulk crystal substrate with predetermined intervals therebetween and between said source and drain regions, one of said source and drain regions comprising a cylindrical region disposed inwardly from said gate fingers and the other of said drain and source regions comprising an annular region disposed outwardly from and surrounding said gate fingers, said gate fingers including at least one current permeable aperture so that a channel current flowing between said source and drain regions flows through the aperture and transverse to the thickness of said semi-insulating semiconductor bulk crystal substrate; and a gate contacting electrode electrically contacting said gate and spaced from said bulk crystal substrate.

Claim 18

A permeable base transistor comprising: a semi-insulating semiconductor bulk crystal substrate having a thickness; source and drain regions highly doped relative to said bulk crystal substrate spaced from and opposite each other in said semi-insulating semiconductor bulk crystal substrate; a semiconductor gate having a low resistance relative to said bulk crystal substrate comprising a plurality of gate fingers disposed along a circle within said bulk crystal substrate with predetermined intervals therebetween and between said source and drain regions, one of said source and drain regions comprising a cylindrical region disposed inwardly from said gate fingers and the other of said drain and source regions comprising an annular region disposed outwardly from and surrounding said gate fingers, said gate fingers including at least one current permeable aperture so that a channel current flowing between said source and drain regions flows through the aperture and transverse to the thickness of said semi-insulating semiconductor bulk crystal substrate; and a gate contacting electrode electrically contacting said gate and spaced from said bulk crystal substrate.

Claim 19

A permeable base transistor as defined in claim 14 wherein said plurality of gate fingers are disposed along a circumference of several hundreds of microns with an interval of about 0.1 to 10 microns between adjacentt gate fingers and the gate length is less than 0.5 micron.