US5057443A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for fabricating a trench bipolar transistor
Assignee: Texas Instruments Inc
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Filing: 1990-05-14
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Granted: 1991-10-15
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Expires: 2010-05-14
Abstract
Abstract A bipolar transistor formed in a trench depression such that a single impurity diffusing step is effective to form a buried collector layer electrically connected to a vertical collector conductor. The lateral diffusion forming the vertical collector conductor is effective to form the conductor with a uniform vertical doping profile, thereby reducing non-uniform series collector resistance characteristics. A trench depression sidewall dielectric is formed, and the trench is filled with a transistor silicon material by a selective epitaxial process. Base and emitter region are then formed in the collector epitaxial material.
Inventors
- 👤 Louis N. Hutter
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:13
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/40; H10D62/00; H10D62/10; H10D62/13; H10D62/137; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/018; H10W10/10; H10W20/00; H10W20/01; H10W20/021
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
90 words
A method for fabricating bipolar transistor, comprising the steps of: forming a trench depression in a semiconductor substrate; forming a heavily doped layer of semiconductor material as a shell around said trench depression; forming an insulating layer on the sidewalls of said trench depression, a bottom portion of said trench depression being defined by said heavily doped shell; forming a semiconductor collector material in a lower portion of said trench depression; forming a semiconductor base material in said collector material; and forming a semiconductor emitter material in said base material.
Claim 2
Independent Claim
90 words
A method for fabricating bipolar transistor, comprising the steps of: forming a trench depression in a semiconductor substrate; forming a heavily doped layer of semiconductor material as a shell around said trench depression; forming an insulating layer on the sidewalls of said trench depression, a bottom portion of said trench depression being defined by said heavily doped shell; forming a semiconductor collector material in a lower portion of said trench depression; forming a semiconductor base material in said collector material; and forming a semiconductor emitter material in said base material.
Claim 3
Dependent Claim
30 words
The method of claim 1, further including forming a heavily doped collector contact region outside said dielectric layer in said substrate and in electrical contact with said heavily doped shell.
Claim 4
Dependent Claim
24 words
The method of claim 1, further including forming said transistor in an area of said substrate comprising no more than about fifty square microns.
Claim 5
Dependent Claim
24 words
The method of claim 1, further including forming said transistor in an area of said substrate comprising no more than about thirty square microns.
Claim 6
Dependent Claim
27 words
The method of claim 1, further including forming a plurality of said transistors adjacent each other, and forming a semiconductor collector conductor common to each said transistor.
Claim 7
Dependent Claim
18 words
The method of claim 5, further including forming a single vertical collector conductor central to each said transistor.
Claim 8
Dependent Claim
18 words
The method of claim 5, further including forming each said transistor as an octagonal cell in said substrate.
Claim 9
Dependent Claim
20 words
The method of claim 1, further including forming a low resistance silicide surface on the sidewalls of the trench depression.
Claim 10
Independent Claim
93 words
A method for fabricating a bipolar transistor adapted for improved current carrying capability, comprising the steps of: forming a trench depression in a semiconductor substrate; forming a heavily doped semiconductor collector region adjacent sidewalls of said trench depression, said heavily doped collector region having a substantially uniform vertical doping profile so that incremental resistance changes thereof as measured in a vertical direction are substantially uniform; forming a semiconductor collector material within said trench depression; forming a semiconductor base region within said collection material; and forming a semiconductor emitter region within said base region.
Claim 11
Independent Claim
93 words
A method for fabricating a bipolar transistor adapted for improved current carrying capability, comprising the steps of: forming a trench depression in a semiconductor substrate; forming a heavily doped semiconductor collector region adjacent sidewalls of said trench depression, said heavily doped collector region having a substantially uniform vertical doping profile so that incremental resistance changes thereof as measured in a vertical direction are substantially uniform; forming a semiconductor collector material within said trench depression; forming a semiconductor base region within said collection material; and forming a semiconductor emitter region within said base region.
Claim 12
Dependent Claim
27 words
The method of claim 9, further including forming an insulating layer defining a dielectric between said collector material and a portion of said heavily doped collector region.
Claim 13
Dependent Claim
30 words
The method of claim 10, further including forming said collector material as an epitaxial deposit of semiconductor material which is laterally isolated from said substrate by said insulating dielectric layer.
Claim 14
Dependent Claim
16 words
The method of claim 10, further including forming said insulating layer as a cylindrically shaped structure.
Claim 15
Dependent Claim
36 words
The method of claim 9, further including forming said heavily doped collector region within said trench depression so as to define a shell of heavily doped material on the sidewalls and bottom of said trench depression.
Claim 16
Dependent Claim
18 words
The method of claim 13, further including forming said dielectric only on the sidewalls of said trench depression.
Claim 17
Dependent Claim
26 words
The method of claim 13, further including forming a vertical part of said collector region at the same time as said bottom collector region is formed.
Claim 18
Dependent Claim
24 words
The method of claim 9, wherein said collector region is formed by a lateral diffusion of impurities into the sidewalls of said trench depression.
Claim 19
Dependent Claim
34 words
The method of claim 9, further including forming a semiconductor resistor within one of said base region or said emitter region, and further including forming a channel stop providing surface isolation to said resistor.
Claim 20
Dependent Claim
20 words
The method of claim 9, further including forming a low resistance silicide surface on the sidewalls of said trench depression.
Claim 21
Independent Claim
144 words
A method for processing a semiconductor wafer to form different channel stop areas in different areas of the wafer, comprising the steps of: forming a blanket implant of a first impurity over the surface of the wafer to form a surface channel stop; forming trench depressions in the surface of the wafer to define transistor operating areas; covering the surface of the semiconductor wafer with a masking material; anisotropically etching the semiconductor wafer to uniformly remove the masking material so that the bottoms of the trench depressions are removed of substantially all said masking material; selectively growing an epitaxial semiconductor material within said trench depressions; and blanket implanting the surface of the wafer so that a second impurity is driven into the surface of the epitaxial semiconductor material but not into other masked surface areas of the wafer previously implanted with said first impurity.
Claim 22
Independent Claim
144 words
A method for processing a semiconductor wafer to form different channel stop areas in different areas of the wafer, comprising the steps of: forming a blanket implant of a first impurity over the surface of the wafer to form a surface channel stop; forming trench depressions in the surface of the wafer to define transistor operating areas; covering the surface of the semiconductor wafer with a masking material; anisotropically etching the semiconductor wafer to uniformly remove the masking material so that the bottoms of the trench depressions are removed of substantially all said masking material; selectively growing an epitaxial semiconductor material within said trench depressions; and blanket implanting the surface of the wafer so that a second impurity is driven into the surface of the epitaxial semiconductor material but not into other masked surface areas of the wafer previously implanted with said first impurity.
Claim 23
Dependent Claim
54 words
The method of claim 19, further including covering the semiconductor wafer with a first masking material utilized for forming said trench depressions, and then forming a second masking material over the surface of the wafer so that the surface of the wafer has a thicker masking material than the bottoms of said trench depressions.
Claim 24
Dependent Claim
14 words
The method of claim 19, wherein said first and second implant impurities are different.
Claim 25
Dependent Claim
24 words
The method of claim 19, wherein said first implant impurity is an acceptor type impurity, and said second implant impurity is a donor-type impurity.
Claim 26
Dependent Claim
27 words
The method of claim 19, further including masking the wafer with a dielectric, and said anisotropic etch forms a sidewall dielectric on sidewalls of said trench depressions.
Claim 27
Dependent Claim
27 words
The method of claim 19, further including forming channel stop areas of said first and second implants with different type impurities and without a photoresist masking step.
Claim 28
Dependent Claim
20 words
The method of claim 19, further including forming said second implant self-aligned in said epitaxial material using said masking material.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-14 | 1995-04-15 | 1995-10-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-14 | 1999-04-15 | 1999-10-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-14 | 2003-04-15 | 2003-10-15 | $7700.00 | Window Closed / Lapsed |