Patent US5055896A successfully refreshed from Google Patents.
US5055896A
Expired / Lapsed
US
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Self-aligned LDD lateral DMOS transistor with high-voltage interconnect capability
Assignee: Vishay Siliconix Inc
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Filing: 1988-12-15
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Granted: 1991-10-08
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Expires: 2008-12-15
Abstract
Abstract Our invention is an annular-shaped or rectangular-shaped lateral DMOS device which overcomes the problems of field crowding caused by a high voltage drain interconnect line creating an increased electric field in the vicinity of a drift region/channel interface. To prevent the interconnect line voltage from causing field crowding, the drift region is discontinued for a portion under the interconnect line so as to make that part of the DMOS device inactive. Therefore, the portion of the DMOS device under the high voltage drain interconnect is not subject to field crowding and in no way reduces the breakdown voltage of the DMOS device. In one embodiment of this invention, a field oxide region is formed between a channel region and a drain region in an area under and extending out from under where a high voltage drain interconnect is to be formed. Impurities implanted in a subsequent impurity implant process to form the drift region will, therefore, be prevented from entering the silicon under the field oxide region.
Inventors
- 👤 Richard K. Williams
- 👤 Steven H. Bolger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 12:22
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/601; H10D30/603; H10D30/01; H10D30/021; H10D30/0221; H10D30/64; H10D30/66; H10D30/668; H10D62/00; H10D62/10; H10D62/102; H10D62/103; H10D62/105; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/299; H10D62/307; H10D64/00; H10D64/111
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
239 words
An annular-shaped or rectangular-shaped DMOS transistor comprising: a substrate of a first conductivity type having a top surface; a drain region of a second conductivity type formed on and below said top surface of said substrate; a drift region of a second conductivity type formed on and below said top surface of said substrate, said drift region contacting and substantially surrounding said drain region; a body region of a first conductivity type formed on and below said top surface of said substrate, said body region surrounding said drift region and being separated from said drift region by a portion of said substrate; a source region of a second conductivity type formed within said body region; a gate oxide layer formed on said top surface of said substrate over a channel region between said source region and a termination point of said drift region; a control gate formed over said gate oxide layer; a first electrode contacting and shorting together said body region and said source region; a second electrode contacting said drain region and forming an interconnect line extending over a portion of said control gate, said body region, and said source region; and an inactive region located in an area under said interconnect line and extending out from under said interconnect line, said inactive region being an area where said drift region terminates at a distance from said channel region to reduce field crowding under said interconnect line.
Claim 2
Dependent Claim
239 words
An annular-shaped or rectangular-shaped DMOS transistor comprising: a substrate of a first conductivity type having a top surface; a drain region of a second conductivity type formed on and below said top surface of said substrate; a drift region of a second conductivity type formed on and below said top surface of said substrate, said drift region contacting and substantially surrounding said drain region; a body region of a first conductivity type formed on and below said top surface of said substrate, said body region surrounding said drift region and being separated from said drift region by a portion of said substrate; a source region of a second conductivity type formed within said body region; a gate oxide layer formed on said top surface of said substrate over a channel region between said source region and a termination point of said drift region; a control gate formed over said gate oxide layer; a first electrode contacting and shorting together said body region and said source region; a second electrode contacting said drain region and forming an interconnect line extending over a portion of said control gate, said body region, and said source region; and an inactive region located in an area under said interconnect line and extending out from under said interconnect line, said inactive region being an area where said drift region terminates at a distance from said channel region to reduce field crowding under said interconnect line.
Claim 3
Dependent Claim
99 words
The DMOS transistor of claim 1 further including circuit means for applying a voltage between said source region and said drain region, said circuit means at least intermittently applying a voltage V DS between said source region and said drain region, the voltage applied between said source region and said drain region never exceeding V DS , wherein the smallest distance between said drift region and said interconnect line at a point where said drift region terminates at said channel region under said gate, expressed in microns, is equal to or greater than V DS divided by 15 volts.
Claim 4
Dependent Claim
51 words
The DMOS transistor of claim 1 wherein said inactive region is formed by an oxide region overlying said substrate interposed between said channel region and said drift region, said oxide region being thicker than said gate oxide layer, at least a portion of said control gate extending over said oxide region.
Claim 5
Dependent Claim
21 words
The DMOS transistor of claim 3 wherein said inactive region comprises a region of said substrate of said first conductivity type.
Claim 6
Dependent Claim
57 words
The DMOS transistor of claim 1 wherein the smallest distance between said drift region and said interconnect line at a point where said drift region terminates at said channel region under said gate is such that voltage breakdown will not occur in said DMOS transistor solely by reason of said field crowding produced by said interconnect line.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1994-10-07 | 1995-04-08 | 1995-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-07 | 1999-04-08 | 1999-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-07 | 2003-04-08 | 2003-10-08 | $7700.00 | Window Closed / Lapsed |