Patent US2978069A successfully refreshed from Google Patents.
Patent US5053357A successfully refreshed from Google Patents.
US5053357A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of aligning and mounting an electronic device on a printed circuit board using a flexible substrate having fixed lead arrays thereon
Assignee: NXP USA Inc
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Filing: 1990-08-14
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Granted: 1991-10-01
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Expires: 2010-08-14
Abstract
Abstract An electronic component having a flexible substrate with conductive traces thereon may have the leads separated into arrays that are shaped to contact and be surface mounted to the bonding lands on a printed circuit board (PCB). The flexible substrate, such as polyimide, adheres to the traces and is formed into lead arrays with them. The lead arrays thus keep portions of the leads and the outer bonding areas corresponding thereto aligned with respect to each other during handling and mounting to the PCB. An alignment mechanism may be optionally present on the lead arrays that mates with a corresponding mechanism on the PCB. The package body itself may be overmolded, assembled from prior parts, etc. Another alternative version includes test points on the perimeter of the substrate beyond the outer bonding areas that may be used to test the device, such as an integrated circuit chip or die, at an intermediate stage in the assembly process. The periphery and test points may be sheared away before the package is mounted to the PCB. A variety of outer bonding area pitches may be provided on the same package with test points of a standard pitch. The relatively inexpensive device is thin and easily mounted by conventional techniques.
Inventors
- 👤 Paul T. Lin
- 👤 Michael B. McShane
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 19:14
CPC Classifications
H; H10; H10P; H10P74/00; H05; H05K; H05K3/00; H05K3/30; H05K3/303; H10W; H10W70/00; H10W70/60; H10W70/67; H10W70/688; H10W74/00; H10W74/10; H10W74/111; H10W74/114; H05K2201/00; H05K2201/10; H05K2201/10227; H05K2201/10295; H05K2201/10303; H05K2201/10613; H05K2201/10621; H05K2201/10681; H05K2203/00; H05K2203/16; H05K2203/162; H05K2203/167; H10W72/00; H10W72/851; H10W72/874; H10W72/884; H10W72/90; H10W72/931; H10W72/932; H10W90/00; H10W90/701; H10W90/731; H10W90/734; H10W90/751; H10W90/754; Y; Y02; Y02P; Y02P70/00; Y02P70/50; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49004; Y10T29/49117; Y10T29/49121
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
218 words
A method for making an electronic device suitable for surface mounting on a printed circuit board (PCB) having bonding lands comprising: providing an insulative, flexible substrate having a periphery, where the substrate has an electronic component receiving area thereon; and where the substrate additionally has a plurality of electrically conductive traces thereon extending from the electronic component receiving area to the periphery, where the traces have inner bonding areas near the electronic component receiving area; and outer bonding areas near the periphery; affixing an electronic component having a plurality of bonding pads thereon to the electronic component receiving area on the substrate; electrically connecting the bonding pads to the inner bonding areas; surrounding at least the electronic component and the inner bonding areas with a package body; providing slots in the flexible substrate to separate the plurality of traces into at least two groups of traces, each of the groups being fully supported along the entire length of the traces by the flexible substrate, and each of the groups being provided with means for aligning the traces of the group to lands on a PCB; and forming the at least two groups of traces into lead arrays to permit the outer bonding areas to contact and be bonded as a group to the bonding lands on a PCB.
Claim 2
Independent Claim
218 words
A method for making an electronic device suitable for surface mounting on a printed circuit board (PCB) having bonding lands comprising: providing an insulative, flexible substrate having a periphery, where the substrate has an electronic component receiving area thereon; and where the substrate additionally has a plurality of electrically conductive traces thereon extending from the electronic component receiving area to the periphery, where the traces have inner bonding areas near the electronic component receiving area; and outer bonding areas near the periphery; affixing an electronic component having a plurality of bonding pads thereon to the electronic component receiving area on the substrate; electrically connecting the bonding pads to the inner bonding areas; surrounding at least the electronic component and the inner bonding areas with a package body; providing slots in the flexible substrate to separate the plurality of traces into at least two groups of traces, each of the groups being fully supported along the entire length of the traces by the flexible substrate, and each of the groups being provided with means for aligning the traces of the group to lands on a PCB; and forming the at least two groups of traces into lead arrays to permit the outer bonding areas to contact and be bonded as a group to the bonding lands on a PCB.
Claim 3
Dependent Claim
62 words
The method of claim 1 further comprising the step of providing a test point along each trace, where the test point is at the substrate periphery further removed from the electronic component receiving area than the outer bonding areas, and where the device is tested by probing the test points after the electronic component is electrically connected to the inner bonding areas.
Claim 4
Dependent Claim
36 words
The method of claim 2 further comprising the step of severing the test points and periphery from the portion of the substrate containing the outer bonding areas and the package body after the device is tested.
Claim 5
Dependent Claim
63 words
The method of claim 1 further comprising the steps of surface mounting the device to a PCB, and where after the forming of the lead arrays, the device is aligned to the PCB with the means for aligning on at least one of the lead arrays and the traces of the group are bonded to the lands of the PCB as a group.
Claim 6
Independent Claim
277 words
A method for making an electronic device suitable for surface mounting on a printed circuit board (PCB) having bonding lands comprising: providing an insulative, flexible substrate having a periphery, where the substrate has an electronic component receiving area thereon; and where the substrate additionally has a plurality of electrically conductive traces thereon extending from the electronic component receiving area to the periphery, where the traces have inner bonding areas near the electronic component receiving area; outer bonding areas near the periphery; and test points, where the test point is at the substrate periphery further removed from the electronic component receiving area than the outer bonding areas; affixing an electronic component having a plurality of bonding pads thereon to the electronic component receiving area on the substrate; electrically connecting the bonding pads to the inner bonding areas; surrounding at least the electronic component and the inner bonding areas with a package body; testing the package by probing the test points after the electronic component is surrounded with the package body; providing slots in the flexible substrate to separate the plurality of traces into at least two groups of traces, each of the groups being fully supported along the entire length of the traces by the flexible substrate, and each of the groups being provided with means for aligning the traces of the group to lands on a PCB; forming the at least two groups of traces into lead arrays to permit the outer bonding areas to contact and be bonded to the bonding lands on a PCB; and severing the substrate periphery containing the test points from the substrate having the outer bonding areas and the package body.
Claim 7
Independent Claim
277 words
A method for making an electronic device suitable for surface mounting on a printed circuit board (PCB) having bonding lands comprising: providing an insulative, flexible substrate having a periphery, where the substrate has an electronic component receiving area thereon; and where the substrate additionally has a plurality of electrically conductive traces thereon extending from the electronic component receiving area to the periphery, where the traces have inner bonding areas near the electronic component receiving area; outer bonding areas near the periphery; and test points, where the test point is at the substrate periphery further removed from the electronic component receiving area than the outer bonding areas; affixing an electronic component having a plurality of bonding pads thereon to the electronic component receiving area on the substrate; electrically connecting the bonding pads to the inner bonding areas; surrounding at least the electronic component and the inner bonding areas with a package body; testing the package by probing the test points after the electronic component is surrounded with the package body; providing slots in the flexible substrate to separate the plurality of traces into at least two groups of traces, each of the groups being fully supported along the entire length of the traces by the flexible substrate, and each of the groups being provided with means for aligning the traces of the group to lands on a PCB; forming the at least two groups of traces into lead arrays to permit the outer bonding areas to contact and be bonded to the bonding lands on a PCB; and severing the substrate periphery containing the test points from the substrate having the outer bonding areas and the package body.
Claim 8
Dependent Claim
60 words
The method of claim 5 further comprising the steps of surface mounting the device to a PCB, and where after the forming of the lead arrays, the device is aligned to the PCB with the means for aligning on at least one of the lead arrays and the traces of the group are bonded to the lands of the PCB.
References Cited (Backward Citations)
US3718969A
Cited
US3911568A
Cited
US4411719A
Cited
US4742431A
Cited
US4792532A
Cited
JPS6365635A
Cited
US4744009A
Cited
US4783719A
Cited
US4766670A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-09-30 | 1995-04-01 | 1995-10-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-09-30 | 1999-04-01 | 1999-10-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-09-30 | 2003-04-01 | 2003-10-01 | $7700.00 | Window Closed / Lapsed |