Phase adjustment circuit

Claim 2

A phase adjustment circuit using a broad band circuit for adjusting phases of data with each other on a plurality of time divisional high speed highways having different phases, said data including a plurality of frames each of which comprises m bits, m being an integer greater than 1, and having respective frame pulses, said phase adjustment circuit comprising: means for providing a master frame pulse based on a frame pulse selected from the respective frame pulses in the high speed highway and delayed in phase by a maximum amount for detecting a time divisional highway having a phase having the greatest delay; means for providing a master clock based on a high speed highway clock corresponding to said master frame pulse; and means for receiving said plurality of high speed highway data corresponding to said master clock and said master frame pulse.

Claim 3

A phase adjustment circuit using a broad band circuit for adjusting phases of data with each other on a plurality of time divisional high speed highways having different phases, said data including a plurality of frames each of which comprises m bits, m being an integer greater than 1, and having respective frame pulses, said phase adjustment circuit comprising: parallel deploying means for converting k bits, equal to a maximum phase difference between the time divisional high speed highways, into a parallel signal, k being an integer greater than or equal to 1; control means for receiving a clock and a frame pulse from respective ones of the time divisional high speed highways and producing a clock necessary for said parallel deploying means based on the clock and frame pulse; latch means for receiving said parallel signal from said parallel deploying means; maximum delay detecting means for receiving the clock and frame pulse from said control means and selecting the clock and frame pulse having the greatest phase delay, for detecting a time divisional highway having a phase having the greatest delay and outputting the selected clock and frame pulse as the master clock and master frame pulse, respectively; and clock generating means for generating a clock enabling said latch means to receive said parallel signal from said parallel deploying means based on the master clock and master frame pulses output from said maximum delay detecting means and for applying said clock to said latch means.

Claim 4

A phase adjustment circuit using a broad band circuit for adjusting phases of data with each other on a plurality of time divisional high speed highways having different phases, said data including a plurality of frames each of which comprises m bits, m being an integer greater than 1, and having respective frame pulses, said phase adjustment circuit comprising: parallel deploying means for converting k bits, equal to a maximum phase difference between the time divisional high speed highways, into a parallel signal, k being an integer greater than or equal to 1; control means for receiving a clock and a frame pulse from respective ones of the time divisional high speed highways and producing a clock necessary for said parallel deploying means based on the clock and frame pulse; latch means for receiving said parallel signal from said parallel deploying means; maximum delay detecting means for receiving the clock and frame pulse from said control means and selecting the clock and frame pulse having the greatest phase delay, for detecting a time divisional highway having a phase having the greatest delay and outputting the selected clock and frame pulse as the master clock and master frame pulse, respectively; and clock generating means for generating a clock enabling said latch means to receive said parallel signal from said parallel deploying means based on the master clock and master frame pulses output from said maximum delay detecting means and for applying said clock to said latch means.

Claim 5

A phase adjustment circuit according to claim 2, further comprising a plurality of master clock registers, wherein said parallel deploying means, said control means, and said latch means are provided in respective ones of said plurality of master clock registers.

Claim 6

A phase adjustment circuit according to claim 2, wherein said latch means converting the parallel signal to a serial signal at a serial output clock generated by said clock generating means and outputting said serial data.

Claim 7

A phase adjustment circuit according to claim 2, wherein said parallel deploying means comprises: serial parallel converting means for receiving serial data from a first clock applied from said control means and outputting the parallel signal; and storing means for receiving the parallel data from said serial parallel converting means at a second clock applied from said control means to be outputted to said latch means.

Claim 8

A phase adjustment circuit according to claim 3, wherein said maximum delay detecting means detects a predetermined highway and selects the clock and frame pulse applied from said control means of said master clock register corresponding to the highway which has the greatest delay with respect to data on the predetermined highway.

Claim 9

A phase adjustment circuit according to claim 6, wherein said maximum delay detecting means comprises: set/reset flip-flops corresponding to respective highways and reset by a frame pulse obtained by said control means, based on a signal applied from the predetermined highways; a first flip-flop corresponding to respective highways and set by the frame pulse obtained by said control means to which the signal is applied from respective highways; and selecting means for selecting the clock and frame pulse of said control means by determining a particular highway to be subjected to the maximum delay when all the outputs of the flip-flops are set except for the one corresponding to the particular highway.

Claim 10

A phase adjustment circuit according to claim 7, wherein said set/reset flip-flops are set by differential means for detecting a rising edge or a falling edge of the frame pulse applied by said control means corresponding to the predetermined highway.

Claim 11

A phase adjustment circuit according to claim 8, wherein said differential means comprises: a modulo J counter for counting the clocks being reset by the frame pulse and having an enabling terminal for receiving a carry output; a second flip-flop for receiving a carry output of said modulo J counter at its input terminal and for receiving a signal of the input terminal at the clock and AND gate for receiving the output of said second flip-flop at its input gate, whereby said set/reset flip-flops are reset by a variation when said modulo J counter counts J clocks.

Claim 12

A phase adjustment circuit according to claim 7, wherein said maximum delay detecting means further comprises: an AND gate for receiving the output of said set/reset flip-flops by excluding the output corresponding to a particular highway; and a third flip-flop for receiving the output of said AND gate at the frame pulse of the corresponding highway, whereby the output of said third flip-flop controls said selection means.

Claim 13

A phase adjustment circuit according to claim 7, wherein said maximum delay detecting circuit comprises: first detecting means provided in accordance with a plurality of highways and for detecting a frame pulse of respective highways; memory means corresponding to a plurality of highways for storing the output of said first detecting means corresponding to a highway other than a particular highway, in synchronization with the frame pulse of the particular highway; second detecting means for detecting that the output of said memory means corresponding to highways other than the particular highway is already set when the frame pulse corresponding to the particular highway is input; means for resetting said first detecting means at every predetermined clock pulse of the predetermined highway; and means for outputting the frame pulse and clock having the greatest delay among the frame pulse and clock in said plurality of highways in accordance with the output of said second detecting means as the master frame pulse and master clock.