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US5051573A
Expired / Lapsed
US
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Optical logic operation system
Assignee: Hamamatsu Photonics KK
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Filing: 1989-11-14
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Granted: 1991-09-24
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Expires: 2009-11-14
Abstract
Abstract A plurality of ultra-high speed light receiving elements are provided each of which has two rectifier junctions being connected to each other opposite in polarity and has a substantially symmetrical electrode arrangement. A bias voltage is applied to each of the light receiving elements from one or a plurality of power sources. Electrical signals produced by the light receiving elements in response to input optical pulse signals are superposed on one another to produce one or a plurality of output electrical signals representing a predetermined logic operation with respect to the input optical pulse signals. Depending on the arrangement of its elements, the optical logic operation system functions as an OR circuit, AND circuit, NOT circuit, EXCLUSIVE OR circuit, or half-adder circuit.
Inventors
- 👤 Yoshihiko Mizushima
- 👤 Kazutoshi Nakajima
- 👤 Toru Hirohata
- 👤 Takashi Iida
- 👤 Yoshihisa Warashina
- 👤 Kenichi Sugimoto
- 👤 Hirofumi Kan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 16:07
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/14
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
180 words
An optical logic operation system comprising: two light receiving elements connected at a first output-side connection point, said two light receiving elements being responsive to respective two input optical pulse signals for producing two respective electrical signals, each of said two light receiving elements comprising two Schottky electrodes formed on a semiconductor substrate with a predetermined gap therebetween and with a substantially symmetrical arrangement; two power sources for providing bias voltages of opposite polarity to said two light receiving elements at terminals opposite to said first output-side connection point; a SUM output terminal connected to said first output-side connection point and a CARRY output terminal connected to said first output-side connection point; a passive circuit connected to said CARRY output terminal, said passive circuit comprising resistors and capacitors; wherein a SUM output signal and CARRY output signal appear at said SUM output terminal and CARRY output terminal, respectively, each of said SUM output signal and carry output signal comprising a superposition of said two electrical signals and representing a half-adder operation with respect to said two input optical pulse signals.
Claim 2
Dependent Claim
180 words
An optical logic operation system comprising: two light receiving elements connected at a first output-side connection point, said two light receiving elements being responsive to respective two input optical pulse signals for producing two respective electrical signals, each of said two light receiving elements comprising two Schottky electrodes formed on a semiconductor substrate with a predetermined gap therebetween and with a substantially symmetrical arrangement; two power sources for providing bias voltages of opposite polarity to said two light receiving elements at terminals opposite to said first output-side connection point; a SUM output terminal connected to said first output-side connection point and a CARRY output terminal connected to said first output-side connection point; a passive circuit connected to said CARRY output terminal, said passive circuit comprising resistors and capacitors; wherein a SUM output signal and CARRY output signal appear at said SUM output terminal and CARRY output terminal, respectively, each of said SUM output signal and carry output signal comprising a superposition of said two electrical signals and representing a half-adder operation with respect to said two input optical pulse signals.
Claim 3
Dependent Claim
41 words
An optical logic operation system as claimed in claim 1, wherein said passive circuit is connected in parallel with one of said two light receiving elements, and includes a second output-side connection terminal which is connected to said CARRY output terminal.
Claim 4
Dependent Claim
40 words
An optical logic operation system as claimed in claim 1, further comprising two light emitting elements connected to said SUM and CARRY output terminals, respectively, for emitting output optical signals in response to said SUM and CARRY output signals, respectively.
Claim 5
Dependent Claim
28 words
An optical logic operation system as claimed in claim 3, wherein said two light receiving elements and said two light emitting elements are integrated on one semiconductor substrate.
Claim 6
Dependent Claim
22 words
An optical logic operation system as claimed in claim 1, wherein said two light receiving elements are integrated on one semiconductor substrate.
Claim 7
Dependent Claim
22 words
An optical logic operation system as claimed in claim 5 wherein said passive circuit is further integrated on said one semiconductor substrate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-09-23 | 1995-03-25 | 1995-09-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-09-23 | 1999-03-25 | 1999-09-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-09-23 | 2003-03-25 | 2003-09-24 | $7700.00 | Window Closed / Lapsed |